Low Profile Image Sensor Package with Embedded Aperture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current packaging methods for image sensors, such as chip-on-board and shellcase wafer level CSP, face challenges with assembly difficulties, size limitations, yield problems, and limited I/O connections, especially as higher pixel image sensors are used, necessitating a low-profile, cost-effective packaging solution.
Innovation Solution
A low-profile image sensor package is developed, comprising a host substrate assembly with a sensor chip partially embedded in an aperture, featuring multiple circuit layers, contact pads, conductive traces, and a lens module for focusing light onto photo detectors, with a simplified structure that includes a cavity in a third substrate positioned over the photo detectors and electrical connectors linking the contact pads to the conductive traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chip-on-board or shellcase wafer level CSP packaging methods are used, then image sensor modules can be assembled with existing processes, but assembly becomes increasingly difficult and size limitations occur as higher pixel image sensors are used
Solution Approach 1:
The image sensor package is divided into distinct functional components: a sensor chip with photo detectors, a host substrate assembly with circuit layers, and a lens module. This segmentation allows each component to be optimized and manufactured separately using standard processes, then assembled together, reducing overall assembly difficulty while maintaining manufacturability.
Solution Approach 2:
The sensor chip is positioned within an aperture of the host substrate assembly, with the third substrate cavity nesting over the photo detectors. This nested configuration allows compact integration of multiple components in a hierarchical structure, enabling higher pixel density without proportionally increasing assembly complexity.
2Area of stationary object
If standard WLP fan-in packages are used, then chip area equals package area, but the number of I/O connections is limited
Solution Approach 1:
The package design transitions from a planar fan-in configuration to a three-dimensional structure with vertical stacking. The host substrate assembly and sensor chip are positioned at different vertical levels, with conductive traces extending through trenches to establish electrical connections. This dimensional change allows increased I/O connections without proportionally increasing the package footprint area.
3Measurement precision
If higher pixel image sensors are used, then image quality and resolution improve, but assembly limitations and size constraints increase
Solution Approach 1:
The package utilizes thin substrate structures with integrated circuit layers and conductive traces that provide flexibility in routing and connection. This flexibility allows the package to accommodate higher pixel density sensors without requiring proportionally more complex assembly procedures, as the thin-film structure can be adapted to various sensor configurations.
4Volume of moving object
If lower profile devices are demanded, then space limitations are overcome and camera module size is reduced, but manufacturing and assembly become more challenging
Solution Approach 1:
Multiple functional elements are merged into integrated structures: the host substrate assembly combines mechanical support, electrical connections, and optical alignment features. The third substrate cavity integrates both protective enclosure and optical path definition. This merging reduces the overall number of discrete components and assembly steps, enabling lower profile devices without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a cost-effective, simplified structure for image sensor packaging that addresses assembly and size limitations, improving electrical performance and reducing chip power consumption while allowing for increased I/O connections, thus facilitating the integration of higher pixel image sensors in smaller form factors.
Implementation Method 1
the lens module includes one or more lenses disposed for focusing light through the third substrate and onto the photo detectors
Implementation Method 2
a plurality of photo detectors formed on or in the second substrate
Data Source
AI summary
A sensor package comprising a host substrate with opposing first and second surfaces, an aperture extending therethrough, circuit layers, and first contact pads. A second substrate at least partially in the aperture has opposing first and second surfaces, a plurality of photo detectors, second contact pads at the second substrate first surface and electrically coupled to the photo detectors, and trenches formed into the second substrate first surface, conductive traces extending from the second contact pads and into the trenches. A third substrate has a first surface mounted to the first surface of the second substrate. The third substrate includes a cavity formed into its first surface and positioned over the photo detectors. Electrical connectors connect the first contact pads and conductive traces. A lens module is mounted to the host substrate for focusing light through the third substrate and onto the photo detectors.