Low Stress Sacrificial Cap Layer for Transistor Annealing
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Solution Overview
Problem
Current semiconductor transistor fabrication processes face challenges in achieving low stress conditions during the source/drain anneal step, which can impact device yield and performance, particularly in NMOS transistors, due to high stress levels in sacrificial cap layers.
Innovation Solution
A low stress sacrificial cap layer comprising a silicon oxide liner film, a low stress silicon film with high hydrogen content, and a silicon nitride film is used, with specific thickness and stress requirements to minimize stress and improve transistor performance, followed by a controlled anneal and etch process to maintain low stress levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional sacrificial cap layer is used during source/drain anneal, then the anneal process can be completed, but high stress levels are generated that degrade transistor performance and reduce device yield
Solution Approach 1:
The sacrificial cap layer is constructed as a composite structure with multiple materials: a low-stress silicon layer (stress < 300 MPa) combined with a silicon nitride layer. This composite structure maintains the sacrificial function while significantly reducing stress levels during anneal, thereby improving device yield without compromising the anneal process completion
Solution Approach 2:
The invention changes the stress parameter of the sacrificial cap layer from conventional high stress levels to low stress levels (< 300 MPa). By controlling the stress parameter through material selection and layer structure optimization, the patent resolves the contradiction between completing the anneal process and minimizing stress-induced performance degradation
2Reliability
If the sacrificial cap layer stress is reduced to improve transistor performance, then drive current increases, but the structural integrity and protective function may be compromised
Solution Approach 1:
The composite structure combines a low-stress silicon layer with a silicon nitride layer, where each material contributes different properties. The silicon layer provides low stress to improve drive current, while the silicon nitride layer reinforces the structure to maintain integrity, thus resolving the contradiction between performance improvement and structural strength
Solution Approach 2:
The sacrificial cap layer is segmented into multiple functional layers with distinct roles. The low-stress silicon layer specifically addresses the stress reduction need for improved drive current, while the silicon nitride layer handles the structural support function, allowing independent optimization of each layer's properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances transistor drive current and device yield by maintaining low stress levels throughout the fabrication process, improving the performance and reliability of NMOS transistors without negatively affecting the microstructure.
Implementation Method 1
a low stress silicon film with high hydrogen content... to minimize stress and improve transistor performance
Data Source
AI summary
A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.