Low Voltage Drive Circuit for Analog Data Transmission

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Solution Overview

Problem

Existing data communication systems face challenges in efficiently transmitting data over a common bus with low voltage drive circuits, particularly in maintaining synchronization and noise immunity while minimizing power consumption and increasing data rate without significant increases in power usage.

Innovation Solution

The implementation of a Low Voltage Drive Circuit (LVDC) that converts digital data into an analog signal with a low-magnitude oscillating component, allowing for low-power, high-data-rate communication by utilizing multiple frequencies for data streams, and synchronizing with a bus clock signal to optimize channel allocation and data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If digital data is transmitted using conventional high-voltage drive circuits, then noise immunity is improved, but power consumption increases significantly

Engineering Contradiction:

Improvenoise immunityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the voltage parameter from conventional high-voltage levels to low-voltage levels (e.g., 1.8V, 1.0V, or lower), fundamentally altering the operating conditions of the drive circuit to reduce power consumption while maintaining acceptable noise immunity through optimized circuit design

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs dynamic voltage switching and adaptive impedance matching that adjusts circuit parameters in real-time based on transmission conditions, allowing the circuit to operate efficiently at low voltages while maintaining signal integrity and noise immunity when needed

Inventive Principle:

Principle #15Dynamics

2Productivity

If data transmission rate is increased in conventional systems, then productivity is improved, but power consumption increases proportionally

Engineering Contradiction:

Improvedata transmission rateVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent utilizes periodic clocked operation with optimized duty cycles and timing, where data is transmitted in synchronized bursts rather than continuous high-rate transmission, allowing the circuit to operate at low power between transmission events while achieving high effective data rates through efficient use of active transmission periods

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent implements dynamic rate adaptation where the transmission rate is adjusted based on channel conditions and power availability, allowing the system to achieve high productivity when conditions permit while consuming minimal power during lower-priority or error-prone transmission periods

Inventive Principle:

Principle #15Dynamics

3Use of energy by moving object

If low voltage drive circuits are used to reduce power consumption, then energy efficiency is improved, but synchronization with bus clock signal becomes difficult

Engineering Contradiction:

Improvepower consumptionVSAvoidsynchronization stability

Core Design Contradiction:

Use of energy by moving objectVSStability of the object's composition

Solution Approach 1:

The patent incorporates feedback mechanisms including phase-locked loops (PLL) and delay-locked loops (DLL) that continuously monitor the phase and frequency relationship between the low-voltage drive circuit output and the bus clock signal, automatically adjusting timing parameters to maintain synchronization despite voltage variations and process variations

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent employs composite timing circuits that combine multiple synchronization techniques (edge-aligned encoding, mid-data transition encoding, and clock recovery circuits) to create a robust synchronization system that maintains stable operation across varying voltage conditions and bus loads

Inventive Principle:

Principle #40Composite materials

4Use of energy by moving object

If analog signals with low-magnitude oscillating components are used, then power consumption is reduced, but signal-to-noise ratio deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoidnoise susceptibility

Core Design Contradiction:

Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent optimizes the amplitude parameter of the analog signal to a specific low-magnitude level that balances power consumption and noise immunity, using differential signaling and common-mode rejection techniques to maintain signal-to-noise ratio even at reduced voltage levels

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs dynamic signal conditioning including adaptive gain control and variable impedance matching that adjusts the signal amplitude and impedance characteristics in real-time to maintain optimal signal-to-noise ratio across different transmission conditions while keeping average power consumption low

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250103530A1Low voltage drive circuit for transmitting analog data at different oscillation rate

Publication Date: 2025.03.27 SIGMASENSE LLC

AI summary

A low voltage drive circuit (LVDC) includes a digital to analog input circuit operable to convert transmit digital data into combined analog outbound data, where the transmit digital data has a data rate based on a host input clock, and where a first portion of the combined analog outbound data has a first oscillation rate based on a first transmit channel clock and a second portion of the combined analog outbound data has a second oscillation rate based on a second transmit channel clock.