Coupled Low-Voltage Level Shifter for Sub-1 ns Switching
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Solution Overview
Problem
Existing level shifters in integrated circuits face limitations in switching time, failing to operate efficiently at low voltage levels, particularly below 0.5 ns, and require complex designs that occupy significant semiconductor die space.
Innovation Solution
A novel level shifter design incorporating a coupling stage with PMOS transistors and capacitors, capable of operating with VDDL as low as 0.75V, achieves faster switching times by utilizing overdriving voltages to efficiently transition between voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If prior art level shifter designs are used, then the circuit can operate at standard voltage levels, but the switching time cannot be reduced below 0.5 ns and may exceed 1 ns
Solution Approach 1:
The patent changes the voltage parameter by introducing an overdriving voltage signal that exceeds the standard logic voltage levels. This overdriving approach modifies the transistor operating conditions to achieve faster switching times below 0.5 ns while maintaining reliable operation through controlled voltage scaling in the coupling stage.
Solution Approach 2:
The patent implements dynamic voltage scaling where the coupling stage adapts voltage levels in real-time. The dynamic adjustment of voltage signals allows the circuit to optimize switching speed for each transition while maintaining compatibility with standard logic levels at the output, resolving the contradiction between speed and reliability.
2Speed
If complex level shifter designs are used to achieve faster switching, then switching time decreases, but the semiconductor die space occupied increases
Solution Approach 1:
The patent segments the level shifter into two functional stages: a coupling stage that handles voltage scaling and overdriving, and a standard level shifting stage that performs the actual level conversion. This segmentation allows the speed-critical functions to be isolated in a compact coupling stage, reducing overall die space while maintaining fast switching performance.
Solution Approach 2:
The patent adds a temporal dimension to the voltage signal by introducing time-dependent overdriving voltage sequences. This allows the circuit to achieve faster switching without increasing spatial complexity, as the speed improvement comes from optimized voltage timing and magnitude in the coupling stage rather than from additional parallel circuit paths.
3Use of energy by moving object
If low voltage operation is implemented to reduce power consumption, then power efficiency improves, but the circuit fails to operate reliably when peak voltage is insufficient to fully turn on transistors
Solution Approach 1:
The patent applies preliminary action by pre-charging coupling capacitors to elevated voltage levels before the actual switching event. This preliminary voltage preparation ensures that when the switching transistor needs to turn on, sufficient voltage is already available at the gate to fully activate the transistor, maintaining reliability even during low voltage operation and reducing power consumption.
Solution Approach 2:
The patent employs periodic voltage boosting cycles where the coupling stage periodically charges capacitors to overdrive voltages in preparation for upcoming switching events. This periodic action allows the main logic circuit to operate at lower average voltages (reducing power consumption) while ensuring peak voltages are available when needed for reliable transistor switching.
Data Source
AI summary
An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75 V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.