Low-k Gate Spacer Stack for Oxidation-Resistant FinFET Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, parasitic capacitance of dielectric components in semiconductor structures becomes a significant issue, leading to lower device speed and RC delays, and existing methods to reduce parasitic capacitance have not been entirely satisfactory.
Innovation Solution
The implementation of a bi-layer dielectric structure comprising a first dielectric layer of boron nitride with a low-k dielectric constant and high density, and a second dielectric layer that is oxygen-free and less easily oxidized, deposited in the same process chamber, to form gate spacers, inner spacer features, and isolation structures, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If separation distances between active device regions are reduced to meet design requirements of smaller technology nodes, then functional density increases, but parasitic capacitance increases leading to lower device speed
Solution Approach 1:
The patent changes the dielectric constant parameter of the insulating material from conventional high-k materials to low-k materials (k<3.5, preferably k<2.5), which directly reduces parasitic capacitance and improves device speed while maintaining reduced separation distances for high functional density
Solution Approach 2:
The patent employs composite dielectric structures combining multiple low-k dielectric layers with different dielectric constants, and integrates low-k dielectric materials with specific etch selectivity characteristics to create a multi-functional composite system that simultaneously reduces capacitance and enables precise patterning
2Reliability
If conventional dielectric materials are used to maintain structural integrity, then manufacturing reliability is maintained, but parasitic capacitance remains high
Solution Approach 1:
The patent fundamentally changes the dielectric constant parameter from conventional values (k>3.5) to low-k values (k<3.5, preferably k<2.5), achieving up to 50% reduction in parasitic capacitance while maintaining structural integrity through optimized material composition and cross-linking density
Solution Approach 2:
The patent utilizes porous low-k dielectric materials with controlled porosity (20-70% void volume) to reduce effective dielectric constant, where the porous structure lowers parasitic capacitance while maintaining mechanical strength through appropriate pore size distribution and matrix material selection
3Speed
If low-k dielectric materials are used to reduce parasitic capacitance, then device speed improves, but the materials may be more susceptible to oxidation and fabrication damages
Solution Approach 1:
The patent creates composite structures with low-k dielectric layers protected by oxidation-resistant capping layers (such as nitride or oxide layers), forming a multi-layer composite that simultaneously achieves low parasitic capacitance and protection against oxidation and fabrication damages
Solution Approach 2:
The patent employs inert atmospheric processing conditions during fabrication and storage to prevent oxidation of low-k dielectric materials, and designs the low-k materials themselves with inherent oxidation resistance through chemical composition optimization
4Manufacturing precision
If advanced patterning techniques are used to achieve precise gate spacers and inner spacer features, then manufacturing precision improves, but process complexity increases
Solution Approach 1:
The patent applies different dielectric constant values and material compositions to different spatial locations within the insulating structure, with specific low-k materials targeted at regions requiring precise patterning for gate spacers and inner spacers, enabling enhanced local resolution without uniformly complicating the entire process
Solution Approach 2:
The patent divides the insulating structure into multiple segmented low-k dielectric layers with different patterning characteristics, allowing each layer to be optimized for specific fabrication requirements and enabling sequential patterning steps that achieve high precision while managing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhancing device performance by improving gate control, reducing off-state current, and minimizing short-channel effects while sustaining potential fabrication damages.
Implementation Method 1
a first dielectric layer of boron nitride with a low-k dielectric constant
Implementation Method 2
deposited in the same process chamber
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.