LPTEOS-Silicon Nitride Capacitor Low-Temperature Fabrication
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Solution Overview
Problem
Current capacitor fabrication methods, such as the Oxide-Nitride-Oxide (ONO) structure, require high-temperature processes that can cause semiconductor device shifting and metal layer peeling, limiting the integration level and capacitance value, especially in 0.5 μm or below processes.
Innovation Solution
A capacitor structure using a low pressure tetraethyl orthosilicate (LPTEOS) - silicon nitride - LPTEOS intermediate dielectric layer fabricated by low pressure chemical vapor deposition at lower temperatures, replacing the ONO structure, with an optional metal or metallized silicon layer, to maintain high capacitance and prevent device shifting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the LPTEOS layer thickness is reduced to increase capacitance value, then the unit capacitance value increases, but the breakdown voltage is significantly lowered
Solution Approach 1:
The patent uses a composite dielectric structure consisting of LPTEOS layer and silicon nitride layer. The silicon nitride layer has high dielectric constant and high breakdown voltage characteristics, while the LPTEOS layer provides good interface properties. This composite structure achieves both high capacitance density and high breakdown voltage by combining the advantages of different materials.
Solution Approach 2:
The patent changes the material composition and layer thickness parameters of the dielectric stack. By optimizing the thickness ratio between LPTEOS and silicon nitride layers, and adjusting the deposition parameters, the structure achieves high capacitance density without compromising breakdown voltage, resolving the contradiction between capacitance enhancement and reliability maintenance.
2Quantity of substance
If the ONO structure with high capacitance value is used, then the unit capacitance value increases to more than 1.61 fF/μm2, but high temperature treatment is required which causes device shifting and metal layer peeling
Solution Approach 1:
The patent changes the deposition temperature parameter from high temperature (900-920°C required for ONO) to low temperature (620-700°C for LPTEOS). This parameter change allows achieving high capacitance density without subjecting the device to high temperature stress, thereby preventing device shifting and metal layer peeling while maintaining fabrication feasibility.
Solution Approach 2:
The LPTEOS layer acts as an intermediary material that enables low-temperature fabrication. By using LPTEOS deposited at 620-700°C instead of requiring high-temperature oxidation processes, the patent introduces a intermediate deposition method that protects temperature-sensitive components while still achieving the desired dielectric properties for high capacitance density.
3Manufacturing precision
If conventional high temperature oxidation methods are used to grow oxide layers, then the dielectric quality is improved, but a large amount of heat is produced causing all devices to suffer from shifting
Solution Approach 1:
The patent replaces the thermal oxidation process (heat-based) with chemical vapor deposition (chemistry-based). Instead of using high-temperature oxidation to grow dielectric layers, the patent uses LPTEOS deposition at lower temperatures, substituting a thermal process with a chemical deposition process that achieves comparable or superior dielectric quality without excessive heat generation.
Solution Approach 2:
The patent changes the temperature parameter from high temperature (900-920°C for oxidation) to low temperature (620-700°C for CVD). This parameter change maintains dielectric quality through controlled chemical deposition while dramatically reducing heat production, preventing device shifting and enabling better process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new capacitor achieves a higher unit capacitance value and maintains excellent breakdown voltage while reducing heat-induced issues, allowing its application in 0.5 μm or below processes without device shifting or metal layer peeling.
Implementation Method 1
A capacitor structure using a low pressure tetraethyl orthosilicate (LPTEOS) - silicon nitride - LPTEOS intermediate dielectric layer fabricated by low pressure chemical vapor deposition at lower temperatures
Data Source
AI summary
A capacitor and a method of fabricating thereof are provided. A structure of low pressure tetraethyl orthosilicate—low pressure silicon nitride—low pressure tetraethyl orthosilicate is used in the capacitor to replace the oxide-nitride-oxide structure of the existing capacitor; the capacitor has a relatively high unit capacitance value. Furthermore, the structure of low pressure tetraethyl orthosilicate—low pressure silicon nitride—low pressure tetraethyl orthosilicate is fabricaited by low pressure chemical vapor deposition method at relatively low temperature; thus the heat produced in the whole process is relatively low, which is insufficient to make the semiconductor device shift or make the gate metal layer or the metallized silicon layer peel off. Accordingly, the capacitor and the method of fabricating the capacitor of the present invention can be well applied in the process of the 0.5 μm PIP capacitor or below 0.5 μm.