LTPS Array Substrate Layout With Fewer Photomasks and Integrated Vias
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Solution Overview
Problem
The manufacturing of low temperature poly-silicon thin film transistor array substrates requires a large number of photomask processes, leading to increased costs and reduced competitiveness due to complex processes and additional requirements for integrating touch panels.
Innovation Solution
The solution involves replacing the planarization layer with an interface layer, using one photomask-process to form heavily-doped and lightly doped areas through gate re-etching, and simultaneously forming deep and shallow vias in the interface and passivation layers, reducing the number of photomasks needed from 10 to 8 and addressing parasitic capacitance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low temperature poly-silicon thin film transistor array substrate is manufactured using conventional processes, then electrical performance and mobility are improved, but the number of photomask processes increases to 9-12, resulting in increased costs and decreased competitiveness
Solution Approach 1:
The patent merges multiple separate photomask processes into fewer integrated steps. Specifically, the gate electrode formation and source/drain electrode formation are combined into a single photomask process, and the via formation for pixel electrode and common electrode connection is achieved through integrated etching steps. This merging reduces the total photomask count from 9-12 to 6-7 processes while maintaining the required electrical performance through optimized electrode structures and materials.
Solution Approach 2:
The patent employs universal electrode structures that serve multiple functions. The gate electrode and source/drain electrodes are designed with materials and configurations that simultaneously provide electrical conduction, mechanical support, and integration with touch panel functions. This multi-functionality allows a single electrode structure to fulfill multiple roles, reducing the need for separate specialized processes and photomasks.
2Adaptability or versatility
If touch panel is integrated into low temperature poly-silicon thin film transistor array substrate, then functionality is improved, but additional photomask process is required, increasing the total to 11 photomask-processes
Solution Approach 1:
The patent merges the touch panel electrode formation with the existing TFT electrode formation processes. The pixel electrode and common electrode structures are integrated into the same photomask and etching processes used for TFT source/drain electrodes. This merging allows touch panel functionality to be added without requiring separate dedicated photomask processes, thereby maintaining competitiveness while achieving multi-functionality.
3Shape
If planarization layer with larger thickness is used, then surface flatness is improved, but multiple etching processes with multiple photomasks are required to form vias
Solution Approach 1:
The patent extracts the planarization function from a separate thick planarization layer and integrates it into the interface layer formed between the TFT structure and the transparent conductive layers. This interface layer provides the necessary surface flatness while being thin enough to allow via formation through integrated etching processes. By taking out the planarization function and embedding it in the interface layer, the patent eliminates the need for multiple separate etching processes while maintaining surface quality.
Data Source
AI summary
A display panel, an array substrate, and a manufacturing method thereof, wherein the array substrate includes a thin film transistor device, and an interface layer, a first transparent conductive layer, a passivation layer, and a second transparent conductive layer which are formed on the thin film transistor device in sequence. By replacing a planarization layer in the prior art with the interface layer, performing a gate re-etching process, and perforating the interface layer and the passivation layer to simultaneously form a deep via and a shallow via, a number of photomasks required to form the array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks.