LTPS Array Substrate Through Hole Patterning for Etching Quality
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Solution Overview
Problem
The manufacturing process of high-PPI LTPS array substrates is complex due to the need for two separate through holes with different etching times, leading to overetching or underetching issues when attempting to simplify the process by forming both through holes in a single patterning step.
Innovation Solution
The method involves forming a first through hole to connect the shielding layer and source/drain electrode layer, and a second through hole at the same position as the first, along with third through holes to connect active layers and source/drain electrode layers, all in a single patterning process, ensuring consistent etching quality and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two separate patterning processes are used to form through holes with different depths, then etching quality is maintained, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the through hole formation into two distinct patterning processes: a first patterning process forms through holes through the first insulating layer to connect the anode, and a second patterning process forms through holes through the second insulating layer to connect the cathode. This segmentation allows each etching process to be optimized independently for its specific depth requirement, maintaining etching quality while managing process complexity through systematic division of the manufacturing steps.
2Device complexity
If one patterning process is used to form both types of through holes, then manufacturing process is simplified, but etching quality deteriorates due to overetching or underetching
Solution Approach 1:
The patent divides the through hole formation into separate first and second patterning processes, where the first process etches through the first insulating layer to a first depth, and the second process etches through the second insulating layer to a second depth. This segmentation prevents overetching or underetching by allowing each process to be independently controlled and optimized for its specific depth requirement.
Solution Approach 2:
The first patterning process is performed preliminarily to form through holes to a first depth, creating a foundation structure. Subsequently, the second patterning process is performed to form through holes to a second depth. This preliminary action approach allows each etching process to build upon the previous one, ensuring proper depth control and preventing overetching or underetching.
3Reliability
If additional storage capacitance is added to compensate for reduced storage capacitance area in high-PPI products, then display performance is improved, but device structure complexity increases
Solution Approach 1:
The patent implements a dual-use shielding layer that serves multiple functions: it acts as a shielding layer for electromagnetic interference protection and simultaneously functions as an additional storage capacitance structure. The anode and cathode are both connected to this shielding layer, creating storage capacitance between them. This multi-functionality approach compensates for reduced storage capacitance area in high-PPI products without significantly increasing device structure complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach guarantees etching quality while reducing the number of patterning processes required, preventing overetching or underetching issues and simplifying the manufacturing process for high-PPI LTPS array substrates.
Implementation Method 1
implanting phosphorous ions into the active layers
Implementation Method 2
implanting boron ions into the active layers
Data Source
AI summary
A method for manufacturing an array substrate includes: forming a shielding layer, an insulating buffer layer, active layers, a gate insulating layer and NMOS gate electrodes in a display area and a drive area on a substrate in sequence; forming a PMOS gate electrode in the drive area on the foregoing substrate, in which the NMOS gate electrodes and the PMOS gate electrode are provided on the same layer; meanwhile forming a first through hole in a common electrode connecting area, in which the first through hole is configured to connect the shielding layer and a source/drain electrode layer; forming an intermediate insulating layer on the foregoing substrate, forming a second through hole in the common electrode connecting area and third through holes in the display area and the drive area, in which the second through hole is formed at a same position as the first through hole and configured to connect the shielding layer and a source/drain electrode layer, and the third through holes are configured to connect the active layers and the source/drain electrode layer; and forming the source/drain electrode layer on the foregoing substrate.