LTPS Pixel Structure Fabrication via Grey-Tone Masking
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Solution Overview
Problem
The conventional fabrication process of low temperature poly-silicon thin film transistors (LTPS TFTs) is complex and costly, requiring multiple mask processes and resulting in poor conductive characteristics due to shielding of the poly-silicon pattern during doping, which restricts the design of storage capacitors.
Innovation Solution
A simplified fabrication method for a pixel structure using a half-tone or grey-tone mask process to pattern semiconductor and conductive layers, allowing self-alignment of lightly doped regions and direct contact between source/drain patterns and regions, reducing the number of processing steps and avoiding misalignment issues, while incorporating a storage capacitor design that improves aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional multi-mask processes are used to form pixel structure, then manufacturing precision can be maintained, but device complexity and production cost increase significantly
Solution Approach 1:
The patent combines multiple mask processes into a single mask step by using a carefully designed mask pattern that defines multiple features simultaneously. The mask pattern includes openings positioned to form the semiconductor pattern, lightly doped regions, and other structural elements in one exposure and development cycle, eliminating the need for sequential masking operations.
Solution Approach 2:
The mask pattern is segmented into multiple functional regions with different opening configurations. Each segment serves a specific purpose: some openings align with the substrate to form semiconductor patterns, while others create lightly doped regions. This segmentation allows a single mask to perform multiple patterning functions that traditionally required separate mask steps.
2Reliability
If poly-silicon pattern is shielded by lower electrode pattern during doping, then structural integrity is maintained, but conductive characteristic deteriorates
Solution Approach 1:
The patent performs doping operations before forming the lower electrode pattern. By conducting ion implantation or diffusion doping in earlier process steps when the poly-silicon pattern is exposed, the semiconductor regions achieve proper dopant concentration and electrical conductivity before the lower electrode is deposited. This preliminary doping action eliminates the shielding problem that would occur if doping were attempted after electrode formation.
3Productivity
If traditional storage capacitor design is used, then manufacturing process is simplified, but aperture ratio and display quality are limited
Solution Approach 1:
The patent integrates the storage capacitor function into the existing pixel structure by utilizing vertical stacking and lateral positioning within the same planar area. The capacitor electrodes are formed using the same conductive layers and insulation structures as the transistor, stacking capacitor elements above and below the active pixel region. This dimensional integration allows the storage capacitor to occupy minimal area while maintaining full functionality, thereby increasing the aperture ratio without adding process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies the fabrication process, enhances process throughput, reduces production costs, and improves display quality by allowing more efficient storage capacitor design and alignment, resulting in favorable pixel structure characteristics.
Implementation Method 1
The ELA process mainly uses the laser beam to irradiate an amorphous silicon layer (a-Si layer), such that the a-Si layer is recrystallized after melting to form a poly-silicon layer
Implementation Method 2
the a-Si layer is recrystallized after melting to form a poly-silicon layer
Data Source
AI summary
A fabrication method of a pixel structure includes providing a substrate. A semiconductor layer and a first conductive layer are formed on the substrate in sequence and patterned to form a semiconductor pattern and a data line pattern. A gate insulation layer and a second conductive layer are formed on the substrate in sequence and patterned to form a gate pattern and a scan line pattern connected to each other. A source region, a drain region, a channel region, and a lightly doped region are formed in the semiconductor pattern. A third conductive layer formed on the substrate is patterned to form a source pattern and a drain pattern. A protective layer is formed on the substrate and patterned to form a contact window to expose the drain pattern. A pixel electrode electrically connected to the drain pattern through the contact window is formed on the protective layer.