LTPS Thin Film Transistor Gate Isolation Layer Design
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Solution Overview
Problem
The short channel effect and hot carrier effect in LTPS TFTs due to strong electrical fields at the drain end reduce reliability and stability, and existing methods like LDD or Offset structures require additional photolithography processes or may decrease switch on current.
Innovation Solution
A manufacturing method for LTPS thin film transistors that includes a transition region between the channel and drain contact regions, with a thicker gate isolation layer above the transition region to weaken the electrical field, eliminating the need for an additional LDD process and reducing production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDD or Offset structure is introduced to reduce short channel effect and hot carrier effect, then reliability is improved, but manufacturing complexity increases due to additional photolithography process or alignment offset
Solution Approach 1:
The gate isolation layer serves dual functions: as the standard gate isolation structure and as the transition region structure (equivalent to LDD or Offset) that reduces short channel effect and hot carrier effect. By making the gate isolation layer thickness vary across the transition region, the patent combines what were previously separate structures into one, eliminating the need for additional LDD photolithography processes and alignment steps while maintaining reliability improvements.
Solution Approach 2:
The gate isolation layer thickness is made non-uniform, being thicker in the transition region compared to other areas. This local variation in thickness creates the desired electrical field weakening effect specifically where needed (at the drain end near the channel) without affecting other regions, thereby improving reliability locally without adding overall device complexity.
2Reliability
If LDD structure is manufactured with additional photolithography process, then short channel effect and hot carrier effect are reduced, but production cost increases
Solution Approach 1:
The gate isolation layer is designed to simultaneously serve as both the gate isolation structure and the transition region structure. This merging eliminates the need for a separate LDD photolithography process, thereby reducing production costs while still achieving the reliability benefits of reduced short channel effect and hot carrier effect through the varied thickness design.
3Reliability
If Offset structure is used to reduce short channel effect, then reliability is improved, but alignment offset may occur reducing manufacturing precision
Solution Approach 1:
By integrating the transition region function into the gate isolation layer itself, the patent eliminates the need for separate Offset structure alignment. The varied thickness is achieved through the same photolithography process that defines the gate, ensuring perfect alignment without additional alignment steps, thereby maintaining both reliability improvements and manufacturing precision.
4Reliability
If gate isolation layer thickness is increased at transition region, then electrical field is weakened reducing hot carrier effect, but device complexity increases
Solution Approach 1:
The gate isolation layer thickness is increased specifically in the transition region to weaken the electrical field and reduce hot carrier effect, while maintaining standard thickness in other regions. This localized modification achieves the desired reliability improvement without significantly increasing overall device complexity, as it utilizes the existing gate isolation layer rather than adding new structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability of LTPS TFTs by reducing hot carrier and short channel effects while maintaining switch on current, and simplifies the manufacturing process by omitting the LDD process.
Implementation Method 1
the gate isolation layer above the transition region is thicker than the channel region and can weaken the electrical field of the channel region close to drain
Implementation Method 2
The effects, such as hot carrier effect caused thereby will influence the reliability and stability of the element
Data Source
AI summary
The present invention provides a manufacture method of a LTPS thin film transistor and a LTPS thin film transistor. The gate isolation layer is first etched to form the recess, and then the gate is formed on the recess so that the width of the gate is slightly larger than the width of the recess. Then, the active layer is implemented with ion implantation to form the source contact region, the drain contact region, the channel region and one transition region at least located between the drain contact region and the channel region. The gate isolation layer above the transition region is thicker than the channel region and can shield a part of the gate electrical field to make the carrier density here lower than the channel region to form a transition.