Semiconductor LUN Selection Cycle for Lower Command Overhead

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Solution Overview

Problem

Existing semiconductor systems face increased command overhead and complexity in NAND flash memory systems due to the use of serial command address interfaces, which affect performance and require complex internal circuits for parallel operations.

Innovation Solution

Implementing a logical unit number (LUN) selection cycle in semiconductor systems, where a selection signal is transmitted before command and address signals, allowing for reduced command overhead and simplified internal circuits by eliminating unnecessary address cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If NAND interface method is used to transmit command and data through the same bus, then device complexity is reduced, but command overhead increases and performance deteriorates

Engineering Contradiction:
Improvedevice complexityVSAvoidperformance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the transmission process into distinct cycles: LUN selection cycle, command cycle, address cycle, and data cycle. This segmentation allows command overhead to be processed separately from data transmission, improving performance without requiring complex parallel circuits.

Inventive Principle:
Principle #1Segmentation

2Productivity

If SCA interface method is used to transmit command and data through different buses, then command overhead is reduced, but internal circuit complexity increases for parallel operations

Engineering Contradiction:
Improvecommand overheadVSAvoidinternal circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements periodic action by using separate cycles for different operations: LUN selection cycle for device selection, command cycle for command transmission, address cycle for address transmission, and data cycle for data transfer. This periodic structure reduces command overhead while avoiding the need for complex parallel circuits.

Inventive Principle:
Principle #19Periodic action

3Loss of information

If multiple address cycles are used for data input operations, then address transmission is completed, but command overhead increases by up to five cycles

Engineering Contradiction:
Improveaddress transmissionVSAvoidcommand overhead
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent applies preliminary action by transmitting the LUN selection signal in advance during a dedicated LUN selection cycle before the command and address cycles. This preliminary selection reduces the number of address cycles needed from five to one, significantly reducing command overhead while ensuring proper device selection.

Inventive Principle:
Principle #10Preliminary action

4Loss of information

If multiple address cycles are used for data output operations, then address transmission is completed, but command overhead increases by three cycles

Engineering Contradiction:
Improveaddress transmissionVSAvoidcommand overhead
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent uses preliminary action by establishing device selection through the LUN selection signal in advance. This allows the system to reduce address cycles from three to one for data output operations, decreasing command overhead while maintaining proper address transmission functionality.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12424271B2Semiconductor apparatus and semiconductor system having lun selection cycle, and operating method of semiconductor system
Publication Date: 2025.09.23 SK HYNIX INC
  • US12424271B2 patent drawing
  • US12424271B2 patent drawing
  • US12424271B2 patent drawing

AI summary

A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus transmits a command signal during a command cycle and transmits an address signal during an address cycle. The first semiconductor apparatus transmits a selection signal during a LUN selection cycle before the command cycle. The second semiconductor apparatus performs a data input/output operation based on the selection signal, the command signal, and the address signal.