LUT-Based Neuron Membrane Potential Update for Neuromorphic Speed

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Solution Overview

Problem

Software simulations for neuromorphic systems with Spike Time Dependent Plasticity (STDP) models are computationally intensive, necessitating a hardware-based approach for updating Neuron Membrane Potential (NP) to achieve faster operations and real-time learning.

Innovation Solution

A hardware-based method using digital axon timers, look-up tables (LUTs), and accumulators to approximate analog spike signals, generate intermediately updated NP values, and apply leak decay effects, culminating in a final updated NP value compared to a fire threshold using a comparator.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If software simulation is used for neuromorphic systems with STDP model, then computational accuracy is maintained, but operation speed becomes excessively slow

Engineering Contradiction:
Improveoperation speedVSAvoidlearning cycles per unit time
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent replaces software-based numerical simulation with a hardware-based neuromorphic system that uses electronic circuits to physically implement neuron membrane potential updates. The LUT-based architecture with digital axon timers, accumulators, and comparators substitutes the mechanical/software computation process with parallel hardware operations, achieving approximately 1000x speedup while maintaining STDP model accuracy

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The neuron membrane potential update process is segmented into distinct hardware modules: digital axon timer for spike signal approximation, first LUT and accumulator for intermediate NP value generation, second LUT for leak decay effect, and comparator for threshold comparison. This segmentation enables parallel processing of multiple neurons simultaneously, dramatically increasing learning cycle throughput

Inventive Principle:
Principle #1Segmentation

2Speed

If hardware implementation is used for neuromorphic systems, then operation speed increases significantly, but system complexity increases

Engineering Contradiction:
Improveoperation speedVSAvoidhardware structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements a universal LUT-based architecture where the same hardware structure (axon timer, LUTs, accumulator, comparator) can process multiple different STDP models and neuron types. The look-up tables store pre-computed values that can be configured for different synaptic weight functions and membrane potential dynamics, allowing one hardware design to handle various neuromorphic computations without requiring separate dedicated circuits for each model variant

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces look-up tables as intermediary structures that pre-compute and store complex STDP transformation values. Instead of performing complex real-time calculations for each neuron update, the system uses LUTs to map input parameters (axon timer value, synapse weight) to pre-calculated membrane potential changes, significantly simplifying the real-time hardware computation while maintaining model accuracy

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If real-time learning is achieved through hardware implementation, then practical operation time frame is reduced, but computational resources increase

Engineering Contradiction:
Improvecomputational timeVSAvoidhardware resources
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

The patent performs preliminary computation by pre-calculating and storing STDP transformation values in look-up tables during system initialization or training phases. These pre-computed values represent complex synaptic weight update rules and membrane potential dynamics that would require intensive real-time calculation. By storing these results in LUTs, the system eliminates the need for complex real-time mathematical operations during actual neuromorphic processing, achieving real-time performance with moderate hardware resources

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10748058B2LUT based neuron membrane potential update scheme in STDP neuromorphic systems
Publication Date: 2020.08.18 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10748058B2 patent drawing
  • US10748058B2 patent drawing
  • US10748058B2 patent drawing

AI summary

A method and system are provided for updating a neuron membrane potential in a spike time dependent plasticity model in a Neuromorphic system. The method includes approximating a shape of an analog spike signal from an axon input using a hardware-based digital axon timer. The method further includes generating a first intermediately updated neuron membrane potential value from a current axon timer value, a current synapse weight value and a current neuron membrane potential value using a first look-up table and an accumulator. The method also includes generating a second intermediately updated neuron membrane potential value with a leak decay effect using a second look-up table and the first intermediately updated neuron membrane potential value. The method additionally includes generating a final updated neuron membrane potential value based on a comparison of the second intermediately updated neuron membrane potential value with a neuron fire threshold level using a comparator.