Neural Architectures TRIZ Cases

A cross-layer rescaling method adjusts output and input channel weights to equalize dynamic ranges in neural network layers.

A hybrid convolution operation slides input data in one dimension and output data in another to reduce memory accesses.

A quantization method segments input distributions to generate approximated density functions for determining optimal step sizes.

A tensor deep stacked neural network uses bilinear modeling to map hidden layers via Khatri-Rao products for efficient prediction.

A computer-implemented method trains a classifier using a pretext model to learn semantically meaningful features from unannotated data.

Modular chassis components adapt optical neural network architectures by inserting processing units, resolving static hardware limitations.

A machine learning model predicts binary test results for mobile network quality assessment.

A configurable stacked architecture with programmable datapaths accelerates deep neural network layers through direct data passing between execution units.

A neuron device uses time division multiplexing across series-connected synapse modules to apply coefficient information to input signals.

Segmented variational autoencoders encode mixed data types separately to reproduce statistical properties, resolving privacy constraints and dataset imbalance.

Hierarchical node assembly maintains population diversity and reduces evaluation time compared to flat parameter optimization.

An asymmetric loss function penalizes overprediction of open time to prioritize timely delivery in B2B electronic communications.

A trained artificial neural network reorders layers by displacing the batch normalization layer after the convolution layer.

A sparse recurrent mixture density network uses Lasso-penalized feedforward layers to reduce dimensionality before temporal pattern capture.

A neuromorphic neuron apparatus uses an accumulation block to update a state variable based on input signals and decay behavior.

A bridge transform converts training images into a common domain to enable contrastive learning across visual domains.

A DNN layer operation apparatus splits weighted filters into linear combinations of fixed-point convolution kernels.

A denoising neural network trained with deep feature losses from an audio classifier.

Generative adversarial networks produce synthetic validation data mimicking real sensor distributions, eliminating manual labeling costs.

Hardware-based digital axon timers and look-up tables approximate analog spike signals to generate updated neuron membrane potential values.

The Sifr optimizer uses diagonal Hessian approximations to reduce training duration while maintaining computational efficiency.

Segmented memory dies and an intermediary controller reduce energy consumption and computation time in neural network processing.

Segmenting external driver models from internal factors in supervised learning algorithms to adjust target variables and isolate idiosyncratic effects.

Generating images from encrypted payload and time data enables accurate application identification without deep packet inspection overhead.

An adversarial network system identifies silent features using quantum scoring to build specialized models.

Vertical stacking of spintronic resonators increases neuron density on limited chip surfaces, facilitating fast low-power real-time learning.

A multi-size convolutional layer resizes input channels to match predetermined group sizes before combining them into a single operation.

LSTM models associate object trajectories to resolve occlusion errors while optimizing computational resources.

Optical reservoir computing replaces software algorithms with tunable materials to resolve energy-speed contradictions.

Hierarchical neuron grouping reduces power consumption and transmission inefficiencies by detecting spike events per group rather than individually.

An intermediate representation controller selects hardware compute units using implementation profiles to process microcode primitives.

A bit-serial neural network accelerator processes neurons sequentially to boost computational throughput and energy efficiency.

Hardware-software co-design integrates placement optimization into neural network training, reducing cross-chip traffic and improving runtime performance.

A distributed reinforcement learning training system parallelizes actor and learner components to accelerate model convergence.

A reinforcement learning system trains a Q network using a target Q network to estimate future cumulative rewards.

A neural network updates node weights based on input-output correlation to distribute representations across all nodes.

Attention mechanism in recurrent neural network identifies security breach correlations in user interaction data, resolving analysis complexity bottlenecks.

A method distributes neural network layer computations across multiple processors within an electronic device to optimize resource usage.

A probabilistic neural network propagates input distributions to compute estimated Shapley values.

A cross-entity communication system predicts user actions to streamline notifications among trusted travel businesses.

Recurrent and spatio-temporal architectures capture temporal dependencies to resolve accuracy complexity trade-offs in spoken language understanding.

A computer-implemented method scales pre-trained analog neural network components to generate temporal-coding-based spiking neural network components.

A neural network model generates pseudo-labeled data through teacher-student adaptive matching to expand training datasets.

Backpropagating loss through a fixed decoder enables encoder training on unlabeled data, eliminating the need for costly ground truth labels.

Correlated electron switch elements resolve speed-reliability contradictions by storing synaptic weights through abrupt impedance transitions.

Holistic convolutional neural network detection eliminates character segmentation to maintain accuracy under occlusion, damage, and varying angles.

Segmenting neural network operations across multiple FPGA dies resolves interconnect bandwidth limitations while maintaining processing throughput.

Hybrid neural network system converts voice data to text using convolutional feature extraction and recurrent time-series analysis.

A 3D face pose estimation method locates the nose tip using surface curvature maps to define a detection zone.