NeuroSynaptic Core Placement Algorithm for Inter-Chip Communication Reduction
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Solution Overview
Problem
Existing neural network training frameworks do not adequately consider hardware constraints during network mapping, leading to sub-optimal performance due to inefficient inter-chip communication and resource utilization in multi-chip neurosynaptic systems.
Innovation Solution
The proposed method involves a hardware-software co-design approach that integrates placement optimization into the training process, using the NeuroSynaptic Core Placement Algorithm to determine the physical location of neurosynaptic cores and minimize inter-chip communication by tuning network parameters and structure based on hardware constraints, thereby optimizing corelet construction and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If neural networks are mapped onto multi-chip hardware without considering hardware constraints, then network training and deployment can proceed, but inter-chip communication efficiency deteriorates and resource utilization becomes sub-optimal
Solution Approach 1:
The patent performs placement optimization during the network training phase rather than during deployment. By pre-calculating optimal core placements and mapping neural network layers to specific hardware cores before the network is fully trained, the system eliminates the need for reconfiguration during runtime. This preliminary action ensures that data flows efficiently across the hardware architecture from the start, reducing inter-chip communication overhead while maintaining high productivity.
Solution Approach 2:
The system dynamically adjusts placement parameters and network mapping configurations based on hardware constraints. By changing the mapping parameters that define how neural network operations are distributed across cores and chips, the system optimizes resource utilization and minimizes inter-chip communication requirements, thereby reducing energy loss while maintaining productivity.
2Ease of manufacture
If neural networks are designed without hardware-aware placement optimization, then implementation is simpler, but hardware resource utilization deteriorates
Solution Approach 1:
The patent implements an automated placement optimization system that self-adjusts the mapping between neural network layers and hardware cores. The system uses algorithms to automatically determine optimal placements based on hardware constraints without requiring manual configuration. This self-service approach maintains ease of implementation while dramatically improving hardware resource utilization, as the system autonomously optimizes the mapping during the training phase.
3Adaptability or versatility
If inter-chip communication is not optimized during network mapping, then network training can proceed without additional constraints, but communication efficiency deteriorates
Solution Approach 1:
The system modifies mapping parameters to minimize inter-chip communication requirements. By changing how neural network operations are assigned to specific cores and chips, the system reduces the frequency and volume of data transfers between chips. This parameter optimization maintains network training flexibility while significantly reducing communication time losses.
4Loss of time
If hardware constraints are not considered during network design, then design process is faster, but runtime performance deteriorates
Solution Approach 1:
The patent performs placement optimization during the network training phase, which is a preliminary step before deployment. By addressing hardware constraint considerations during training rather than during deployment, the system maintains a fast design process while ensuring optimal runtime performance. The placement decisions are made in advance based on hardware characteristics, allowing the network to run efficiently without adding complexity to the design workflow.
Data Source
AI summary
Hardware placement of neural networks is provided. In various embodiments, a network description is read. The network description describes a spiking neural network. The neural network is trained. An initial placement of the neural network on a plurality of cores is performed. The cores are located on a plurality of chips. Inter-chip communications are measured based on the initial placement. A final placement of the neural network on the plurality of cores is performed based on the inter-chip communications measurements and the initial placement. The final placement reduces inter-chip communication.