LVDS Input Circuit with Dynamic Common-Mode Voltage Clamping
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Solution Overview
Problem
Low voltage differential signaling (LVDS) circuits face challenges in maintaining reliable operation at high signal speeds due to significant signal loss, variations in circuit operation, and difficulty in generating a stable common mode voltage, especially when common mode voltage varies across the power supply range, leading to thermal noise and increased input current requirements.
Innovation Solution
The implementation of a tracking loop that senses the incoming common mode voltage and compares it to a reference voltage, allowing the input circuitry to adaptively maintain a minimum common mode voltage, eliminating the need for a resistive voltage divider and thereby reducing signal loss, using P-MOSFETs as switched current sources to bias the differential amplifier transistors and ensure sufficient voltage for proper operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a resistive voltage divider network is used to establish common mode voltage, then the transistors are turned on, but significant signal loss occurs
Solution Approach 1:
The patent extracts and removes the resistive voltage divider network from the circuit. Instead of using resistors R3 and R4 to establish common mode voltage, the invention uses active transistor-based circuitry (common mode control circuit) to generate the same effect without the signal loss associated with resistive dividers.
Solution Approach 2:
The patent introduces a common mode control circuit as an intermediary component that actively manages the common mode voltage. This circuit includes transistors and control logic that mediate between the power supply and the differential amplifier, providing stable common mode voltage without requiring a resistive voltage divider.
2Ease of operation
If all-pass input networks with resistances are used, then common mode voltage control is achieved, but thermal noise is introduced and signal losses increase
Solution Approach 1:
The patent replaces the passive resistive all-pass networks with active transistor-based impedance transformation circuitry. The active circuit provides the same common mode control function without the thermal noise generation inherent in resistive networks, effectively substituting a noisier component with a quieter alternative.
3Loss of energy
If multiple gain stages are added to compensate for signal loss, then signal amplitude is restored, but circuit complexity increases
Solution Approach 1:
The patent applies preliminary action by establishing the correct common mode voltage level before the signal enters the differential amplifier stage. The common mode control circuit pre-configures the operating point of the transistors, ensuring optimal signal transmission from the outset and eliminating the need for subsequent gain stages to compensate for losses.
4Adaptability or versatility
If the common mode voltage varies across the power supply range, then the circuit must handle full range variations, but reliable operation becomes difficult to maintain
Solution Approach 1:
The patent implements feedback through the common mode control circuit, which continuously monitors and adjusts the common mode voltage to maintain it within the optimal range regardless of power supply variations. This feedback mechanism ensures that the differential amplifier operates reliably even when the overall power supply voltage changes.
Solution Approach 2:
The patent uses dynamic transistor-based circuitry that can adapt its operating characteristics in real-time. The common mode control circuit dynamically adjusts bias conditions and transistor operating points to maintain consistent differential amplifier performance across varying power supply conditions, replacing static resistive networks with adaptive active components.
Data Source
AI summary
Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling the common mode voltage at the input of an LVDS receiver. The common mode voltage of the incoming LVDS signal is monitored. The common mode voltage at the input of the LVDS receiver is clamped at a clamp voltage when the common mode voltage of the incoming LVDS signal is less than a predetermined voltage, and allowed to track it otherwise.