MAC Input Formatting for High-Precision Binary Throughput
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Solution Overview
Problem
Existing machine learning hardware components, such as multiplier-accumulators (MACs), face challenges in efficiently processing higher resolution data due to predefined bit widths, leading to underutilization and bandwidth constraints, which can result in increased power consumption, circuit area, and thermal issues.
Innovation Solution
Implementing a method where multiplier-accumulators pack multiple data elements into a single bit-augmented word, allowing simultaneous storage and processing of output words across multiple addressable locations, effectively doubling the data throughput without altering the hardware design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If lower bit-width data or components are used, then power consumption is reduced and circuit area is reduced, but precision is reduced
Solution Approach 1:
The patent segments higher precision data (e.g., 16-bit data) into multiple lower precision components (e.g., two 8-bit values). These segmented values are processed separately through the lower precision hardware pipeline, allowing the system to achieve higher effective precision without requiring higher precision hardware components throughout the entire system.
Solution Approach 2:
The patent introduces a new dimension to data representation by packing multiple data elements into a single data structure that can be processed through lower precision hardware. This dimensional transformation allows higher precision computation to be achieved through clever data organization rather than through higher precision hardware alone.
2Measurement precision
If higher precision data processing is implemented, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the lower precision hardware pipeline universal by enabling it to process higher precision data through segmentation and packing techniques. The same hardware infrastructure can handle both lower precision native operations and higher precision augmented operations, eliminating the need for separate higher precision hardware paths.
3Measurement precision
If higher precision data processing is implemented, then measurement precision is improved, but circuit area increases
Solution Approach 1:
The patent merges multiple lower precision data processing operations into a unified higher precision processing framework. By combining segmentation, packing, and coordinate transformation techniques, the system achieves higher precision results using the same physical circuit area that would otherwise be dedicated to lower precision operations.
4Adaptability or versatility
If existing hardware components are reused for higher precision data, then adaptability is improved, but productivity decreases due to bandwidth constraints
Solution Approach 1:
The patent performs preliminary segmentation and packing of higher precision data into a format suitable for lower precision hardware processing before the data enters the hardware pipeline. This preliminary preparation enables the existing hardware to process higher precision data without bottlenecking, as the data is already organized for efficient processing through the available bandwidth.
Data Source
AI summary
Embodiments include systems and methods for special input formatting for binary input data to be able to process the binary input data as smaller binary data. A method can be performed by a circuit comprising a multiplier-accumulator (MAC) for convolving a data structure with weights of a machine learning model. The method includes obtaining first and second values having a first bit-width. The method includes generating, using a multiplication function of the MAC, a first product using the first value and a first predefined weight, the multiplication function, thereby left shifting the first product. The method includes generating, using the multiplication function, an output word using the first product, the second value, and a second predefined weight. The method includes storing, upon receipt of an instruction, a respective first and second portion of the output word to a first and second addressable location.


