Semiconductor Macro Cell Via Placement for Signal Congestion
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Solution Overview
Problem
Conventional semiconductor device designs face congestion issues with signal wiring lines around macro cells, limiting area reduction and layer minimization due to inefficient power supply wiring arrangements and via placement.
Innovation Solution
A semiconductor device design method that computes consumption current in macro cells, defines specific regions for via placement, and optimizes the arrangement of power supply layers and vias to reduce congestion, allowing for area and layer reduction by strategically positioning wiring layers between logic and power supply regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply wiring lines are arranged in a matrix in upper layers and power supply straps are provided above the macro cell, then the macro cell can be supplied with electric power through vias, but signal wiring lines cannot pass through the macro cell region and must detour around it, causing congestion of signal wiring lines
Solution Approach 1:
The power supply wiring structure is segmented into multiple independent power supply straps arranged in a matrix pattern, allowing signal wiring lines to pass through previously occupied regions without interfering with power delivery to the macro cell
Solution Approach 2:
The power supply wiring is transitioned from a planar arrangement to a three-dimensional matrix structure with multiple layers and spacing, creating vertical and horizontal channels that allow signal wiring lines to pass through the macro cell region without congestion
2Power
If vias are arranged to fill the layers of the entire power supply wiring lines for the macro cell region, then power supply efficiency is improved, but the region where the macro cell is disposed becomes blocked and signal wiring lines must extend around the macro cell, increasing the area of the semiconductor device
Solution Approach 1:
The via arrangement is optimized locally within the power supply wiring structure, concentrating vias where needed for power delivery while leaving other regions open for signal wiring line passage, thereby maintaining power efficiency without blocking the macro cell region
Solution Approach 2:
The matrix arrangement of power supply straps acts as an intermediary structure that facilitates both power delivery to the macro cell and passage of signal wiring lines through the region, eliminating the need for signal lines to detour around the macro cell
3Power
If power supply wiring layers for the memory cell are disposed above the controller to achieve maximum efficiency, then power delivery to the memory cell is optimized, but the power supply wiring layers physically interfere with signal wiring lines in the vicinity of the memory cell, further increasing congestion
Solution Approach 1:
The power supply wiring above the controller is segmented into multiple discrete power supply straps arranged in a matrix, creating spaced-apart power delivery paths that do not physically interfere with signal wiring lines while maintaining efficient power delivery to the memory cell
Solution Approach 2:
The power supply wiring structure is elevated to a three-dimensional matrix arrangement with controlled spacing and positioning, allowing signal wiring lines to pass through the region without physical interference while maintaining optimal power delivery efficiency
Data Source
AI summary
A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.