Main Conversion Circuit Gate Driver Layout for Load Balance
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Solution Overview
Problem
Conventional main conversion circuits face issues with upsizing and complication due to the need for multiple gate drivers or additional circuits to manage unbalanced loads across semiconductor devices connected in parallel, leading to reduced service life and electrical performance.
Innovation Solution
A main conversion circuit design where semiconductor devices with lower energizing ability are connected closer to the gate driver, allowing for balanced gate voltage distribution without additional circuits, thereby enhancing electrical performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple gate drivers are prepared for respective semiconductor devices connected in parallel, then load balance is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by strategically positioning semiconductor devices with different energizing abilities at different locations relative to the single gate driver. Devices with lower energizing ability are placed closer to the gate driver, while those with higher energizing ability are placed farther away. This spatial arrangement compensates for the inherent differences in device characteristics, achieving load balance without requiring multiple gate drivers or additional control circuits.
2Reliability
If additional circuits are added to transistors for current recognition, then load balance is improved, but device complexity increases
Solution Approach 1:
The patent extracts the load balancing function from the semiconductor devices themselves and implements it at the system level through strategic device arrangement. Instead of adding current recognition circuits or control logic to individual transistors, the solution removes the need for such additional components by utilizing the physical layout and wiring structure to naturally balance the loads across parallel semiconductor devices.
3Device complexity
If semiconductor devices are aligned in the same direction with single gate driver, then device complexity is reduced, but load balance deteriorates
Solution Approach 1:
The patent applies asymmetry by intentionally creating an asymmetric arrangement of semiconductor devices relative to the gate driver. Rather than uniformly distributing all devices at equal distances, the design places devices with lower energizing ability closer to the gate driver and devices with higher energizing ability farther away. This asymmetric positioning compensates for the inherent asymmetry in device characteristics, achieving load balance while maintaining a simple single-gate-driver architecture.
Data Source
AI summary
A plurality of semiconductor devices (1) are connected in parallel with each other. A gate driver (13) supplies a gate voltage to gates of the plurality of semiconductor devices (1). A gate wire (14,16) are sequentially connected to the gates of the plurality of semiconductor devices (1) from the gate driver (13). An energizing ability of each of the semiconductor devices (1) indicates how easily collector current flows in response to the supplied gate voltage. The plurality of semiconductor devices (1) having a lower energizing ability are connected closer to the gate driver (13).