Mandrel-Assisted Metal Layer Patterning for Void-Free IMD Filling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor device integration increases, the aspect ratio of metal wiring layers also increases, making it difficult for inter-metal dielectric (IMD) materials to completely fill the spaces between metal lines, resulting in voids that degrade device performance and reliability.

Innovation Solution

A semiconductor device fabrication method involving a titanium and titanium-nitride (Ti/TiN) metal layer, an aluminum metal layer, and an indium tin oxide (ITO) layer, which are formed with a lower aspect ratio to facilitate complete filling of inter-wiring spaces by an IMD layer, reducing the number of fabrication steps and preventing void formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the aspect ratio of metal wiring layers is increased to meet minimum conductivity requirements, then the conductivity is improved, but the IMD layer fails to completely fill the spaces between adjacent metal lines, resulting in voids that degrade device performance and reliability

Engineering Contradiction:
Improvedevice reliabilityVSAvoidIMD layer filling completeness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a mandrel layer pattern before the metal layer pattern. This mandrel structure serves as a preliminary framework that guides subsequent material deposition and prevents void formation during IMD layer formation. The mandrel layer is strategically positioned to provide structural support in high-aspect-ratio regions, ensuring complete IMD filling while maintaining the required metal line geometry for conductivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mandrel layer acts as an intermediary structure between the substrate and the metal layer pattern. This intermediate element facilitates the IMD layer deposition process by providing a physical barrier that prevents material collapse and ensures uniform filling of inter-wiring spaces. The mandrel layer mediates the conflict between high aspect ratio requirements and complete filling requirements, allowing both conditions to be satisfied simultaneously

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the pitch of metal wiring is decreased to increase device integration, then the device integration is improved, but the aspect ratio increases making IMD layer formation increasingly difficult

Engineering Contradiction:
Improvedevice integrationVSAvoidIMD layer formation ease
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The mandrel layer pattern is formed in advance with specific geometric characteristics that anticipate the challenges of subsequent IMD layer deposition. This preliminary structure is designed with optimized dimensions and positioning to facilitate material flow and filling during the IMD deposition process, making high-density integration manufacturable despite the increased aspect ratios

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes critical parameters by introducing the mandrel layer with specific thickness, material composition, and geometric configuration. These parameter modifications fundamentally alter the deposition dynamics, enabling complete IMD filling in high-aspect-ratio structures that would otherwise be difficult to manufacture. The mandrel layer parameters are optimized to balance integration density with manufacturing feasibility

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7432203B2Methods for fabricating a metal layer pattern
Publication Date: 2008.10.07 MARVELL ASIA PTE LTD
  • US7432203B2 patent drawing
  • US7432203B2 patent drawing
  • US7432203B2 patent drawing

AI summary

Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/TiN metal layer; forming an indium tin oxide (ITO) layer on the aluminum metal layer; and patterning the ITO layer, the aluminum metal layer, and the Ti/TiN metal layer by photolithography to form a metal layer pattern and to expose a surface of the lower oxide layer, thereby facilitating a process of filling inter-wiring spaces occurring between adjacent lines of a metal layer pattern by producing a metal layer pattern having a reduced aspect ratio.