Many-Core Processing With Stacked Compute-Memory Direct Connections
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Solution Overview
Problem
Existing chip packaging and wiring designs limit data transmission rates and increase chip area due to centralized data transmission and lengthy connection lines, especially in multi-chip systems.
Innovation Solution
A many-core processing apparatus with chips stacked in a vertical manner, where computing cores are connected to storage cores, reducing transmission pressure and increasing bandwidth through direct connections without Through Silicon Via (TSV) technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chips are connected through centralized data transmission, then chip packaging and wiring costs are reduced, but data transmission rate is limited and chip area increases
Solution Approach 1:
The patent divides the data transmission system into multiple parallel channels by connecting computing cores to storage cores through multiple independent connection paths. Instead of centralized transmission through a single bottleneck, data can be transmitted simultaneously through multiple channels, thereby increasing overall transmission rate while maintaining packaging simplicity.
Solution Approach 2:
The patent transitions from two-dimensional planar chip layout to three-dimensional stacked architecture. By vertically stacking computing chips and storage chips with direct connections between them, the system achieves shorter transmission paths and higher bandwidth in the vertical dimension, overcoming the limitations of planar connectivity.
2Adaptability or versatility
If standard input-output interface units are used, then interface compatibility is ensured, but maximum achievable transmission rate is fixed
Solution Approach 1:
The patent implements a universal connection interface that can adapt to different data transmission rate requirements. The interface structure allows flexible configuration of connection parameters such as bus width and clock frequency, enabling the same physical interface to support varying transmission rates without requiring separate dedicated interfaces for each speed tier.
Solution Approach 2:
The patent introduces dynamic adjustment capability to the data transmission interface. The transmission rate can be dynamically changed based on actual data processing needs, allowing the system to optimize performance for different workloads. The interface parameters such as data width and timing can be adjusted in real-time without hardware reconfiguration.
3Speed
If more connection lines are added between chips, then data transmission rate increases, but chip area and wiring complexity increase
Solution Approach 1:
The patent merges multiple connection lines into a unified parallel transmission structure. Instead of adding separate individual connection lines for each data path, the system combines multiple channels into a single integrated connection interface between computing cores and storage cores, achieving high transmission rate without proportionally increasing chip area.
Solution Approach 2:
The patent implements a nested connection structure where multiple data channels are hierarchically organized. The connection interface is designed with nested signal paths that allow multiple data streams to be transmitted through a compact integrated structure, reducing the overall footprint while maintaining high bandwidth capability.
Data Source
AI summary
A many-core processing apparatus, a data processing method, and a device and a medium. The many-core processing apparatus comprises: a first chip and at least one second chip which are arranged in a stacked manner, wherein the first chip comprises a plurality of computing cores, the at least one second chip forms a storage chip group, and the second chip comprises a plurality of storage cores; at least one computing core in the first chip is connected to at least one storage core in the storage chip group.