3D NAND Memory Plug Holes via Marker Layer Etching
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Solution Overview
Problem
The challenge is to develop a nonvolatile semiconductor storage device that achieves miniaturization and high capacity while addressing the increase in electrical resistance due to the size of the device, which existing technologies have not effectively resolved.
Innovation Solution
A nonvolatile semiconductor storage device is designed with a substrate having a stacked portion of conductor and insulation layers, including a marker layer, with semiconductor pillars formed inside memory plug holes through a charge accumulation film, and a method for manufacturing and controlling the device that involves specific etching processes and voltage control to optimize the formation of memory cell transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor storage elements are three-dimensionally arranged to achieve miniaturization and high capacity, then storage density is improved, but electrical resistance increases
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking of conductor layers and insulation layers. Multiple bit lines are arranged in different layers (first bit line in lower layer, second bit line in upper layer), enabling high-density storage while maintaining electrical performance through optimized vertical interconnect geometry
Solution Approach 2:
The patent applies different materials and structures to specific regions: charge accumulation films are formed only in memory plug holes at specific locations, semiconductor pillars are selectively formed in contact with certain conductor layers, and different conductor layers serve different functions (bit lines vs. word lines). This localized optimization improves electrical characteristics while maintaining high density
2Manufacturing precision
If marker layers are introduced to control etching depth and diameter uniformity, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Marker layers are pre-formed within the stacked structure before the memory plug hole etching process. These marker layers serve as depth references that enable precise control of etching termination, ensuring uniform depth and diameter across all memory plug holes. The marker layers are strategically positioned to provide etching stop references at critical depths
Solution Approach 2:
The marker layers act as intermediary elements between the etching process and the final memory structure. They provide a physical reference that mediates the etching depth control, allowing the process to achieve high precision without requiring complex real-time monitoring or adjustment systems
Data Source
AI summary
According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.