Mask Layout Design for Transistor Uniformity in Semiconductor Arrays
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Solution Overview
Problem
The design accuracy of semiconductor circuit devices is compromised due to variations in transistor characteristics influenced by the distance from the well boundary, leading to differences between outermost and inner cells in an array.
Innovation Solution
A semiconductor circuit device design method where cells are arranged in an array with a predetermined distance between the outermost well end and the active region, set to be larger than a calculated value to suppress the effects of resist scatter and reflection, ensuring uniform transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cells are arranged in an array with minimal spacing to increase packaging density, then productivity and area utilization improve, but transistor characteristics vary due to resist scatter and reflection effects from well boundaries
Solution Approach 1:
The patent applies local quality by introducing dummy wells specifically at the outermost positions of the cell array. These dummy wells create a uniform boundary condition only where needed (at the edges), without modifying the internal structure of regular cells. This localized modification ensures that outermost cells have the same well boundary distance as inner cells, achieving characteristic uniformity only where the boundary effect occurs, while maintaining high packaging density throughout the array.
Solution Approach 2:
The patent implements preliminary action by adding dummy wells during the design stage before actual fabrication. These dummy wells are pre-positioned at the outermost cell locations to prevent resist scatter and reflection effects from affecting the actual transistor characteristics. By preparing this protective structure in advance, the patent ensures that when the cell array is fabricated with minimal spacing, the transistor characteristics remain uniform without requiring post-fabrication adjustments.
2Manufacturing precision
If the distance from well boundary to active region is increased to suppress resist effects, then transistor characteristic uniformity improves, but cell area increases reducing packaging density
Solution Approach 1:
The dummy wells are placed only at the outermost cell positions where boundary effects occur, rather than increasing the distance for all cells. This localized approach achieves the necessary characteristic uniformity only where needed, without unnecessarily expanding the area of internal cells that already have sufficient distance from boundaries.
Solution Approach 2:
The dummy wells are identical copies of regular wells, creating a virtual extension of the well array. This copying approach provides the same boundary condition to outermost cells as inner cells experience, achieving characteristic uniformity without requiring physical expansion of the active cell structures.
3Measurement precision
If outermost cells are modified to maintain characteristic uniformity, then design accuracy improves, but device complexity increases
Solution Approach 1:
The modification is applied only to outermost cells through the addition of dummy wells, rather than redesigning all cells. This localized modification maintains design accuracy for affected cells while keeping the majority of the cell array structure unchanged, thus minimizing the increase in overall device complexity.
Solution Approach 2:
The dummy wells are simple copies of existing well structures, using the same geometric and material properties as regular wells. This copying approach maintains design accuracy without introducing complex new structures, materials, or fabrication processes, thereby avoiding significant increases in device complexity.
Data Source
AI summary
In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.