Mask-Programmable Through Die Vias for Stacked IC Interface Tiles
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Solution Overview
Problem
The existing IC die stacking techniques face challenges in efficiently supporting various daughter IC and manufacturing configurations due to differences in TDV and micro-bump formations, leading to time-consuming and costly re-designs of mother ICs for different inter-chip interfaces and manufacturing processes.
Innovation Solution
A method and apparatus for designing a mother IC with interface tiles that include a layout for through-die vias (TDVs) and mask-programmable interconnects, allowing for flexible TDV configurations without altering the electrical configuration of the interface tiles, enabling compatibility with multiple daughter ICs and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the mother IC is re-designed for different daughter ICs and manufacturing processes, then compatibility with various inter-chip interfaces is improved, but design time and cost increase
Solution Approach 1:
The interface tile is segmented into multiple independently configurable components: TDV region, micro-bump region, and interconnect region. Each component can be independently configured through separate mask patterns, allowing the mother IC to adapt to different daughter IC requirements without redesigning the entire interface tile. This segmentation enables modular reconfiguration for different inter-chip interfaces.
Solution Approach 2:
The invention changes physical parameters of the interface tile through different mask patterns, including TDV diameter, micro-bump diameter, pitch, density, and aspect ratio. By varying these parameters through mask programming rather than redesign, the mother IC can accommodate different manufacturing capabilities and interface requirements while maintaining the same physical interface tile structure.
2Adaptability or versatility
If the mother IC is re-designed for different manufacturing processes, then manufacturing capability compatibility is improved, but design cost increases
Solution Approach 1:
The interface tile is designed as a universal structure that can support multiple manufacturing processes and daughter IC configurations. The same physical interface tile can be programmed with different mask patterns to accommodate varying TDV and micro-bump specifications from different fabrication houses, eliminating the need for multiple specialized designs.
Solution Approach 2:
The mask patterns are prepared in advance for different manufacturing configurations, allowing the mother IC to be manufactured once with a universal interface tile design. The appropriate mask pattern is then selected and applied based on the specific manufacturing process and daughter IC requirements, avoiding the need for physical redesign and remanufacturing.
3Reliability
If TDV and micro-bump configurations are customized for each daughter IC, then interface performance is improved, but device complexity increases
Solution Approach 1:
The interface tile configuration is made dynamic through mask-programmable interconnects that can be programmed after manufacturing. The TDV and micro-bump regions maintain fixed physical structures, but the interconnect layer can be dynamically configured through mask patterns to connect different combinations of TDVs and micro-bumps to the interface logic, optimizing performance for different daughter ICs without increasing physical complexity.
Data Source
AI summary
Examples of the invention relate to a method, apparatus, and computer readable medium for designing a mother integrated circuit (IC) configured for stacking with at least one daughter IC. A layout of the mother IC includes at least one interface tile having an electrical configuration for communicating with interface logic of the daughter IC. The method includes: obtaining design rules for through die vias (TDVs) to be formed in the mother IC for implementing connections between the at least one interface tile and a physical interface of the daughter IC; defining a layout of the TDVs in the mother IC according to the design rules; and defining at least one mask for programming interconnect on the mother IC to physically connect the TDVs between the at least one interface tile and the physical interface of the daughter IC without changing the electrical configuration of the at least one interface tile.