Masked Logic Gate Tree with Share Compression for Side-Channel Protection
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Solution Overview
Problem
Existing digital circuits face challenges in preventing side-channel attacks through Boolean masking, particularly due to complexity and latency issues associated with non-linear gates like AND, NAND, OR, and NOR gates, which are not well-suited for leak-free designs.
Innovation Solution
The proposed solution involves a masked logic gate structure using domain-oriented masking (DOM) and low-latency masking (LOLA) techniques, alternatingly implemented in multiple layers of a tree of gates to achieve a balance between reducing latency and complexity, utilizing specific types of compression gates for share compression, such as 4:2 and 9:3 compression gates, and strategically distributing random bits to prevent leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Domain-Oriented Masking (DOM) technique is used to protect against side-channel attacks, then security protection is improved, but latency increases due to synchronization requirements
Solution Approach 1:
The patent segments the masking operation into two distinct types: DOM gates for security-critical operations and LOLA gates for latency-critical operations. This segmentation allows the system to apply the appropriate technique based on the specific computational context, thereby achieving both security and low latency without requiring full synchronization across all operations.
Solution Approach 2:
The patent dynamically selects between DOM and LOLA techniques based on the type of gate being implemented. By making the masking approach adaptive rather than static, the system can optimize for security when using DOM and for speed when using LOLA, resolving the contradiction between security protection and latency.
2Speed
If Low-Latency Masking (LOLA) technique is used to reduce latency, then speed is improved, but complexity increases due to quadratic growth with logic layers
Solution Approach 1:
The patent segments the logic function implementation into multiple layers, with each layer using a limited number of shares (maximum of 4). This segmentation prevents the quadratic complexity growth by limiting the share count at any given layer, while still achieving low latency through the LOLA technique within each layer.
Solution Approach 2:
The patent changes the parameter of share count from an unbounded value to a bounded value (maximum of 4 shares). This parameter change directly addresses the complexity issue by preventing quadratic growth, while the LOLA technique maintains low latency performance.
3Adaptability or versatility
If non-linear gates (AND, NAND, OR, NOR) are used in masked circuits, then functionality is improved, but leakage risk increases making leak-free design difficult
Solution Approach 1:
The patent introduces random values as intermediaries in the non-linear gate operations. These random values are XORed with the inputs or outputs of non-linear gates to mask the actual data being processed. This intermediary mechanism allows non-linear gates to function while preventing direct leakage of sensitive information, thus resolving the contradiction between functionality and leakage protection.
Data Source
AI summary
A masked logic gate protected against side-channel attacks using Boolean masking with d+1 shares for each input variable, where d is an integer at least equal to 1 representing the protection order is described. The masked logic gate includes a first input configured to receive a number of shares yj (j=0, 1, 2 . . . ); a second input configured to receive (d+1)2 shares xi (i=0, 1, 2 . . . ) representative of an intermediate result output by one layer of a tree of gates implementing low-latency masking with a protection order of d; and a (d+1)-share output obtained by applying a logic function of the masked logic gate to the shares of the first and second inputs using domain-oriented masking.