Masked Memory Cell Array Layout for DPA Security
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Solution Overview
Problem
Existing memory circuitry is inefficient in using resources and complex in layout, particularly in high-security applications where differential power analysis attacks are a concern, and current masked memory cell designs require numerous components and bit lines, leading to high energy consumption and chip area usage.
Innovation Solution
The implementation of masked memory cells that utilize logically valid mask signals only for selected memory cells, reducing the number of required components and bit lines by applying invalid mask signals to unaccessed cells, thereby simplifying the layout and reducing energy consumption and chip area through the use of a masked bit-line Muxor and LSB address decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If masked memory cells are implemented with valid mask signals for all cells, then security against differential power analysis attacks is improved, but device complexity and resource usage increase
Solution Approach 1:
The patent applies different mask signal states to different spatial locations (selected vs. unselected memory cells). Valid complementary mask signals (m=1, mq=0 or m=0, mq=1) are applied only to selected memory cells that need security protection, while unselected cells receive invalid mask signals (m=0, mq=0 or m=1, mq=1). This local differentiation provides security where needed while reducing overall complexity.
Solution Approach 2:
The memory cell array is segmented into selected and unselected groups based on address decoding. The mask signal distribution is also segmented, with valid mask signals routed only to selected cells through the masked bit-line Muxor. This segmentation allows the system to maintain security for accessed data while simplifying the state of non-accessed cells.
2Reliability
If valid mask signals are applied to all memory cells, then security is improved, but energy consumption increases
Solution Approach 1:
Energy consumption is reduced by applying valid mask signals only locally to selected memory cells rather than globally to all cells. The mask signal validity is differentiated by location, ensuring security protection only where data is being accessed and stored, thereby eliminating unnecessary energy expenditure in unselected cells.
Solution Approach 2:
Instead of applying mask signals to all memory cells (excessive action), the system applies valid mask signals only to the subset of cells that are currently selected and accessed (partial action). This partial application of masking is sufficient to protect security while significantly reducing the energy burden compared to universal masking.
3Reliability
If valid mask signals are applied to all memory cells, then security is improved, but chip area increases
Solution Approach 1:
The chip area is optimized by confining valid mask signal application to local regions corresponding to selected memory cells. Unselected cells occupy physical space but maintain invalid mask states, allowing compact layout without requiring additional infrastructure for global mask signal distribution across the entire chip.
Solution Approach 2:
The mask bit-line Muxor serves multiple functions: it routes valid mask signals to selected cells, maintains invalid states in unselected cells, and enables address-based selection. This multi-functionality reduces the need for separate dedicated circuits, thereby conserving chip area while maintaining security capabilities.
4Quantity of substance
If masked bit-line Muxor and LSB address decoder are used, then resource usage is reduced, but device complexity increases
Solution Approach 1:
The mask signal distribution network is merged with the address decoding logic through the masked bit-line Muxor. This combined structure uses the same address signals (including LSB) that control memory cell selection to also control mask signal routing. By merging these functions, the patent reduces the total number of separate components while managing complexity through functional integration.
Solution Approach 2:
The LSB address decoder and masked bit-line Muxor are designed to perform multiple functions: address decoding for cell selection and mask signal routing for security. This multi-functionality reduces the overall component count by eliminating redundant circuits, as the same logic structures serve both addressing and masking purposes.
Data Source
AI summary
An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.