Masking Scan Chain Outputs for IC Testing
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Solution Overview
Problem
Compression of scan chain outputs in integrated circuit testing reduces data bandwidth but leads to loss of information, making it difficult to determine the source of faults due to unknown 'X' values, which can interfere with known values and worsen fault coverage, especially in System-on-a-Chip (SOC) designs with increasing complexity.
Innovation Solution
Implementing multiple mask patterns during a single test cycle using multiple mask banks, where different mask patterns are applied in different portions of the test cycle to effectively mask 'X' values, thereby enhancing fault detection and reducing the ambiguity associated with compressed scan outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan chain outputs are compressed into a bit stream to reduce data bandwidth, then data bandwidth is reduced, but information is lost and fault detection capability deteriorates
Solution Approach 1:
The test cycle is divided into multiple portions (first portion, second portion), and different mask patterns are applied to different portions of the compressed scan output. This segmentation allows selective masking of X values in different time intervals, preserving fault detection capability while maintaining compression benefits.
Solution Approach 2:
Multiple mask patterns are loaded into multiple mask banks, and the mask pattern parameters are changed dynamically during the test cycle. By switching between different mask patterns for different portions of the test cycle, the system can adaptively handle X value distribution variations, improving fault detection without sacrificing compression efficiency.
2Reliability
If multiple mask patterns are applied during different portions of the test cycle, then fault coverage is improved, but device complexity increases
Solution Approach 1:
The test circuit periodically switches between different mask patterns stored in multiple mask banks during the test cycle. This periodic action allows comprehensive fault coverage by applying different masking strategies at different intervals, while the automated switching mechanism keeps the added complexity manageable.
Solution Approach 2:
Multiple mask banks store copies of different mask patterns, allowing the test circuit to switch between pre-prepared masking configurations. This copying approach enables complex fault detection strategies without requiring complex real-time mask generation logic, thereby limiting the increase in device complexity.
Data Source
AI summary
A method for masking scan chains in a test circuit of an integrated circuit is disclosed. The test circuit includes multiple mask banks. Different mask patterns are stored in each of the mask banks. A first mask bank of the multiple mask banks is selected and the mask pattern stored in the selected first mask bank is used for masking the output of the scan chains of the test circuit during a first portion of a test cycle. A second mask bank of the multiple mask banks is selected and the ask pattern stored in the selected second mask bank is used for masking the output of the scan chains of the test circuit during a second portion of the test cycle.