Mass Storage I/O Scheduling for Faster Secondary Data Access

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Solution Overview

Problem

Existing computer systems face significant performance impediments due to the slow data transfer rates between main memory and secondary storage, with CPUs often idle while waiting for data from secondary storage, despite advancements in CPU speed and RAM access times.

Innovation Solution

Implementing a system that optimizes I/O operations by using multipacket structures, deferred request scheduling, and transfer maps to improve the sequencing and timing of data access requests, particularly for secondary storage devices like rotating disks and tapes, reducing latency and increasing access speed by an order of magnitude.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional I/O request processing is used, then system simplicity is maintained, but data transfer speed between main memory and secondary storage is limited by inherent delays in secondary storage devices

Engineering Contradiction:
Improvedata transfer speedVSAvoidI/O system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments I/O requests into multiple sub-requests that can be processed in parallel. Each sub-request targets a specific data range or storage location, allowing the system to overlap I/O operations with CPU processing and reduce total wait time by handling multiple operations simultaneously rather than sequentially

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by pre-fetching data that is likely to be needed soon, caching frequently accessed data in faster memory layers, and pre-positioning storage heads on disks before actual data transfer is needed. This reduces latency by preparing data in advance before the CPU actually needs it

Inventive Principle:
Principle #10Preliminary action

2Productivity

If CPU speed is increased, then processing capability is improved, but I/O system performance does not improve proportionally, causing CPU idle time

Engineering Contradiction:
ImproveCPU utilizationVSAvoidCPU idle time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements continuous useful action by overlapping I/O operations with CPU processing through asynchronous I/O and interrupt-driven architectures. The system maintains continuous data flow between storage and memory using buffering and caching mechanisms, ensuring the CPU is rarely idle while data is being transferred from secondary storage

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system dynamically changes parameters such as buffer sizes, cache allocation, and I/O scheduling priorities based on workload characteristics. This allows optimal tuning of the I/O subsystem to match CPU speed and processing patterns, maximizing CPU utilization by adjusting data transfer parameters in real-time

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If data is stored on secondary storage devices, then storage capacity is increased, but access time increases due to inherent delays in rotating disks and magnetic tapes

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements a nested storage hierarchy where secondary storage devices are nested within a multi-layer storage system that includes intermediate caching layers in main memory and faster buffers. This nested structure allows frequently accessed data to be automatically promoted to faster layers while maintaining access to the full capacity of secondary storage, effectively reducing access time without sacrificing storage capacity

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The system performs preliminary actions by pre-loading data from secondary storage into cache memory based on access patterns and predictions. This anticipatory caching reduces access time for future operations by having data ready in faster memory before it is actually needed, bridging the speed gap between secondary storage and CPU

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12613815B2Fast mass storage access for digital computers
Publication Date: 2026.04.28 GEZELTER ROBERT
  • US12613815B2 patent drawing
  • US12613815B2 patent drawing
  • US12613815B2 patent drawing

AI summary

A system for increasing the speed and reducing the time to obtain a required amount of data, from a secondary storage device, for a digital computer, based upon measures to improve the time efficiency of I/O request processing by improving the timing and sequence of transfers to improve the efficiency of mass storage devices.