Master Processor Coprocessor Synchronization via Register Credit Stalling
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Solution Overview
Problem
In microprocessor systems with multiple processing units, existing technologies face challenges in synchronizing operations between a master processor and a coprocessor while maintaining independent operation and resource management, leading to potential resource bottlenecks and inefficiencies.
Innovation Solution
A synchronized register renaming method is implemented, where the master processor sends operations to the coprocessor with an identifier, and the coprocessor schedules and executes them, notifying the master processor upon completion, while maintaining resource allocation maps to manage resources effectively and prevent stalls due to resource limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the master processor sends operations to the coprocessor for independent execution, then execution parallelism and productivity are improved, but resource synchronization complexity and device complexity increase
Solution Approach 1:
The patent introduces resource allocation maps as intermediary data structures that mediate between the master processor and coprocessor. These maps track resource usage and enable automatic stall detection without complex synchronization protocols, resolving the contradiction by providing a simple intermediary mechanism that enables parallel execution while managing resource synchronization automatically.
Solution Approach 2:
The patent implements feedback mechanisms where the master processor continuously monitors the resource allocation maps to detect when resource limits are reached. This feedback triggers automatic stalling of operation issuance, enabling parallel execution up to resource constraints while preventing resource conflicts through real-time monitoring and adaptive control.
2Measurement precision
If the master processor tracks resource usage to prevent overallocation, then resource allocation accuracy is improved, but processing overhead and loss of time increase
Solution Approach 1:
The patent performs preliminary actions by pre-allocating resources and maintaining resource allocation maps before operations are issued to the coprocessor. The master processor checks resource availability in advance using these maps, determining whether to stall operation issuance before the operations are sent. This preliminary resource verification enables accurate resource tracking while minimizing processing overhead by avoiding runtime resource management complexity.
3Speed
If the coprocessor executes operations out of order for efficiency, then execution speed is improved, but synchronization complexity and reliability challenges increase
Solution Approach 1:
The patent segments the resource management system into separate resource allocation maps for different resource types (registers, execution units, etc.). Each map independently tracks specific resource usage, enabling the coprocessor to execute operations out of order while the master processor maintains reliable synchronization by monitoring individual resource segments. This segmentation allows flexible out-of-order execution while preserving synchronization reliability through structured resource tracking.
Data Source
AI summary
Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in the processors. An ideal and an external register allocation map are implemented in the coprocessor. When registers are no longer allocated according to the ideal allocation map and the registers are currently allocated according to the external allocation map, the registers are deallocated in the external map and the number of freed registers is reported to the master. The master increments a free register credit count accordingly, and decrements the credit count by one for each operation issued to the coprocessor. An operation is not issued to the coprocessor unless at least a register is free according to the credit count. The master also throttles coprocessor operation issue based on a credit count corresponding to free scheduler entries available in the coprocessor.