Master-Slave Synchronization for Processing Elements
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Solution Overview
Problem
Existing synchronization methods for processing elements, such as balanced tree synchronization, are resource-intensive, require a large number of gates and wires, and can be cost-prohibitive, limiting the compactness and performance of processing devices, especially as the number of processing elements increases.
Innovation Solution
A synchronization system that uses a sync signal generator to transmit a synchronization signal to a plurality of synchronizers, where each synchronizer counts from a respective count value representative of the time difference between itself and the downstream synchronizer, allowing processing elements to start operations at a similar instance without relying on balanced tree hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If balanced tree synchronization hardware is used, then synchronization reliability is improved, but device complexity and area increase significantly
Solution Approach 1:
The patent extracts the synchronization function from complex balanced tree hardware and implements it through a simplified master-slave architecture where a single master processing element generates synchronization signals that are distributed to multiple slave processing elements. This eliminates the need for complex interconnecting hardware while maintaining synchronization reliability.
Solution Approach 2:
The master processing element serves multiple functions: it generates synchronization signals, distributes them to all slave processing elements, and coordinates their operations. This multi-functional approach replaces the need for dedicated synchronization hardware with a versatile master element that handles all synchronization tasks.
2Reliability
If balanced tree synchronization hardware is used, then synchronization reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive balanced tree hardware structure and replaces it with a cost-effective master-slave architecture that achieves the same synchronization reliability using fewer gates and interconnections, thereby reducing manufacturing costs.
Solution Approach 2:
The patent uses a simple, inexpensive synchronization signal distribution mechanism instead of expensive balanced tree hardware. The synchronization signals are transmitted through standard communication channels rather than dedicated expensive synchronization wiring, reducing overall system cost.
3Productivity
If the number of processing elements increases, then processing capability is improved, but synchronization hardware requirements increase
Solution Approach 1:
The master processing element is designed to handle an arbitrary number of slave processing elements through a universal synchronization signal distribution mechanism. This allows the system to scale to any number of processing elements without increasing synchronization hardware complexity, as the master element dynamically adapts to the number of slaves.
Solution Approach 2:
The synchronization system is designed to be dynamic rather than static. The master processing element can adaptively generate and distribute synchronization signals to a varying number of slave processing elements, allowing the system to scale flexibly without requiring pre-configured hardware for maximum capacity.
Data Source
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AI summary
In an example, a synchronization signal (116, 204, 346, 348, 350, 436) can be transmitted to a plurality of synchronizers (110,112, 114, 200, 326, 328, 330, 332, 34, 336, 338, 340, 426, 428, 430, 432). The plurality of synchronizers can include a plurality of upstream synchronizers (110, 112, 326, 328, 332, 334, 338, 340, 426, 428, 430) and a downstream synchronizer (114, 330, 336, 342, 432). Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value (212) until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements (102, 104, 106, 308, 310, 312, 314, 316, 318, 320, 322, 324) can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.