Master-Slave Digital Voltage Regulators for Power Area Reduction
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Solution Overview
Problem
Conventional switched mode voltage regulators face challenges with high power and area overhead due to multiple independent digital controllers and Analog-to-Digital Converters (ADCs), especially in advanced deep sub-micron technologies, leading to increased dynamic power consumption and implementation difficulties.
Innovation Solution
The implementation of a master-slave architecture for voltage regulation, where a master VR controls one or more slave VRs using digital PWM control data, reducing the need for multiple digital controllers and ADCs, and incorporating shared delay lines and calibration features to improve accuracy and reduce overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple independent digital controllers and ADCs are used in switched mode voltage regulators, then each voltage domain can be controlled independently, but the area and power overhead increase significantly
Solution Approach 1:
The patent combines multiple voltage regulator controllers into a single shared controller that uses time-interleaved ADC sampling to control multiple voltage domains. Instead of having separate ADCs and controllers for each voltage domain, one ADC samples multiple voltage domains at different time intervals, and a single controller processes all samples, thereby reducing the number of ADCs and controllers while maintaining independent control capability.
Solution Approach 2:
The patent implements time-interleaved periodic sampling where a single ADC cycles through sampling multiple voltage domains in a periodic sequence. The ADC samples voltage domain 1 at time t1, voltage domain 2 at time t2, and so on, creating a periodic sampling pattern that allows one ADC to serve multiple voltage domains, reducing hardware overhead while maintaining monitoring coverage.
2Area of stationary object
If a smaller number of time interleaved ADCs and controllers are deployed, then area overhead is reduced, but the ADC and controller clock frequencies must increase leading to higher dynamic power consumption
Solution Approach 1:
The patent dynamically adjusts the sampling rate and clock frequencies based on the specific requirements of each voltage domain. The single ADC operates at a lower clock frequency by spreading samples across multiple time intervals for different voltage domains, rather than requiring high-frequency simultaneous sampling. This dynamic time-multiplexing approach reduces the clock frequency requirements and associated dynamic power consumption.
3Area of stationary object
If time interleaved ADCs are used in advanced deep sub-micron process nodes, then area overhead is reduced, but routing congestion and interconnect impedances increase leading to measurement errors
Solution Approach 1:
The patent introduces local buffer circuits and shielding structures as intermediaries between the ADC sampling nodes and the voltage domains being measured. These intermediary elements isolate the sensitive ADC sampling circuits from the high-frequency switching noise and voltage drops in the power delivery network, thereby maintaining measurement accuracy despite the compact layout required for advanced process nodes.
Data Source
AI summary
Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge; a second bridge to be coupled to a second load; and a second PWM circuit to drive the second bridge, wherein the first PWM circuit is controlled by a first digital word separate from a second digital word, wherein the second PWM circuit is controlled by the second digital, and wherein the second digital word is derived from the first digital word.