Tunable Matching Network Topology for ESD-Safe High Frequencies

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Solution Overview

Problem

Parasitic capacitance to ground impairs high-frequency performance in tunable matching networks, and existing methods struggle to reduce parasitic capacitance while providing adequate protection against electrostatic discharge (ESD) events.

Innovation Solution

Incorporating shunt inductors into the tunable matching network to reduce parasitic capacitance and enhance high-frequency performance, while also providing protection against ESD through a high-pass filter characteristic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If parasitic capacitance is reduced by using smaller capacitors, then high-frequency performance is improved, but ESD protection capability deteriorates

Engineering Contradiction:
Improvehigh-frequency performanceVSAvoidESD protection capability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A dedicated ESD protection circuit is introduced as an intermediary component between the matching network and ground. This separate ESD protection path allows the main matching network capacitors to be minimized for high-frequency performance while the ESD circuit provides robust electrostatic discharge protection through a separate low-impedance path to ground.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If capacitor size is increased to provide ESD protection, then ESD protection capability is improved, but parasitic capacitance increases

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The capacitance function is segmented into two separate components: small matching network capacitors for high-frequency impedance matching with minimal parasitic effects, and a separate ESD protection capacitor specifically dedicated to electrostatic discharge protection. This segmentation allows each component to be optimized for its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

3Reliability

If ESD protection circuit is added, then ESD protection capability is improved, but circuit complexity increases

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The ESD protection circuit is merged with the existing matching network structure by sharing common nodes and ground references. The ESD protection capacitor is connected in parallel with the matching network at strategic points, allowing both functions to coexist within a unified circuit architecture rather than as completely separate systems.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The addition of shunt inductors improves high-frequency performance and maintains acceptable low-frequency tuning, expanding the network's bandwidth and enhancing its ability to withstand ESD events, thereby achieving robust and efficient impedance matching.

Implementation Method 1

Each non-grounded capacitor pin in a matching network has a parasitic capacitance to ground

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

connecting one or more shunt inductors to a tunable matching network exhibiting parasitic capacitance to ground, whereby high-frequency performance of the tunable matching network is improved

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS8680940B2Tunable matching network circuit topology devices and methods
Publication Date: 2014.03.25 WISPRY INC
  • US8680940B2 patent drawing
  • US8680940B2 patent drawing
  • US8680940B2 patent drawing

AI summary

Methods and devices for modifying a tunable matching network are disclosed. In one aspect, a method of modifying a tunable matching network can include connecting one or more shunt inductors to a tunable matching network exhibiting parasitic capacitance to ground, whereby high-frequency performance of the tunable matching network is improved.