Matrix Decimation Streaming Engine for Strided Convolutions
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Solution Overview
Problem
Digital signal processors face challenges with memory bandwidth and scheduling when processing real-time data streams, particularly in applications requiring predictable but non-sequential input data patterns, which can lead to delays in output data transformation.
Innovation Solution
Incorporating a streaming engine that manages data streams by separating elements of a vector of a matrix prior to storage in a register file, facilitating decimation for strided convolutions, and supporting six levels of nested iteration to improve memory bandwidth and data scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a streaming engine is used to manage data streams with complex patterns, then memory bandwidth and data scheduling efficiency are improved, but device complexity increases
Solution Approach 1:
The streaming engine is divided into multiple functional units including an address generation unit, a data formatting unit, and a decimation unit. Each unit handles a specific aspect of data stream processing, allowing the complex function to be broken down into manageable segments that can operate independently and in parallel, thus improving overall productivity without proportionally increasing complexity.
Solution Approach 2:
The streaming engine implements six levels of nested iteration support, where inner iteration loops are contained within outer iteration loops. This nested structure allows complex data patterns to be processed through hierarchical loops, with each level managing a specific dimension of data access, enabling efficient handling of multi-dimensional data streams while maintaining structured control flow.
2Productivity
If elements of a vector of a matrix are separated prior to storage in a register file, then data scheduling efficiency is improved, but processing time increases
Solution Approach 1:
The streaming engine performs preliminary formatting and separation of matrix vector elements before they are stored in the register file. The address generation unit pre-calculates memory addresses and the formatting unit pre-organizes data elements according to the required access pattern. This preliminary processing ensures that when data is scheduled for processing, it is already in the optimal configuration, improving data scheduling efficiency without requiring additional processing time during the main computation.
Solution Approach 2:
A buffer memory is introduced as an intermediary between the memory controller and the register file. The streaming engine writes formatted and separated vector elements to this buffer, which then supplies data to the register file at the required rate. This intermediary structure decouples the writing and reading operations, allowing data separation and formatting to occur without directly blocking the processing timeline.
Data Source
AI summary
A method is described herein. The method generally includes fetching a set of data from a memory coupled to a memory controller. The method generally includes determining a first subset of data from the set of data. The method generally includes determining a second subset of data from the set of data. The method generally includes determining a first element from the set of data. The method generally includes providing a vector including the first subset, the first element, and the second subset, wherein each element of the first subset is disposed in one portion of the vector and each element of the second subset is disposed in another portion of the vector. The method generally includes storing the vector into a register of the memory controller.


