Matrix Multiplication Hardware With Zero-Value Clock Gating
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Solution Overview
Problem
Matrix multiplication operations, especially for large matrices, are time-consuming and inefficient in terms of silicon area and processing power, and existing hardware lacks flexibility to accommodate various matrix sizes and applications.
Innovation Solution
A hardware unit for matrix multiplication utilizing a pipeline architecture with clock-gated storage elements based on zero-value detection, allowing for efficient power consumption by gating storage elements when input data elements or their portions have zero values, and varying mantissa bit widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If storage elements are continuously clocked in pipeline stages, then data processing is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic clock gating of storage elements based on data characteristics. Instead of continuous clocking, the system periodically evaluates whether storage elements should be clocked by detecting zero values in input data. When zero values are detected, clock gating is applied to reduce power consumption while maintaining computational efficiency through selective activation of storage elements.
2Area of stationary object
If all storage elements are always active, then computational efficiency is maintained, but silicon area requirements increase
Solution Approach 1:
The patent applies dynamic clock gating control to storage elements in the pipeline stages. The control logic dynamically determines which storage elements should be clocked based on the input data characteristics, specifically detecting zero values. This dynamic approach allows the system to reduce silicon area utilization by deactivating storage elements when they can be treated as zero, while maintaining computational efficiency when data requires full processing.
3Adaptability or versatility
If fixed mantissa bit width is used, then hardware design is simplified, but adaptability to different matrix sizes is reduced
Solution Approach 1:
The patent implements variable mantissa bit width capability in the hardware unit. The system can adapt the mantissa bit width parameter based on the specific matrix multiplication requirements and data characteristics. This parameter change approach allows the hardware to handle different matrix sizes and precision requirements without requiring complete hardware redesign, thus improving adaptability while managing complexity through configurable parameters.
Data Source
AI summary
Matrix multiplication via a multi-stage pipeline is performed wherein storage elements associated with stages of the pipeline are clock-gated based on data elements thereof known to have or treatable as having a zero value. The storage elements may be clock-gated on a per data element basis based on whether the data element has or can be treated as having a zero value. The storage elements alternatively may be clock-gated on a partial element basis based on the bit width of the data elements. For example, if the bit width of the data elements is less than a maximum bit width then bits related to that data element can be treated as having a zero value and storage elements associated with that data element may not be clocked. In yet other cases the storage elements may be clock-gated on both a per element and a partial element basis.