Matrix Multiplier Block Division for Flexible Neural Network Computing
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Solution Overview
Problem
Current matrix multiplication methods, such as those using vector processors and systolic arrays, are inefficient and inflexible, leading to long computation times and fixed computing sizes, which hinder the performance of convolutional neural networks and other applications that require large data operations.
Innovation Solution
A matrix multiplier is designed with a controller that divides large matrices into smaller sub-blocks, allowing for efficient pipeline execution and full load operation units, using a fractal matrix multiplication method that enables flexible and high-density computation by performing operations on identity matrices in each clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a vector processor is used to compute matrix multiplication, then the computation can be performed using standard sequential methods, but the computation time is long and the computing size is fixed and inflexible
Solution Approach 1:
The patent divides large matrices into smaller sub-matrices (block matrices) that can be processed in parallel. The matrix multiplication C=A*B is segmented into multiple compute units, each handling a specific block of the result matrix. This segmentation enables flexible computing sizes by adjusting the number and size of compute units, while also reducing computation time through parallel processing of these segments.
2Productivity
If a two-dimensional computation array (systolic array) is used to increase computation speed, then the computation speed is improved, but the computing size remains fixed and inflexible
Solution Approach 1:
The patent employs a dynamic architecture where the number of compute units can be configured based on the input matrix sizes. Unlike fixed systolic arrays, this design allows the computing resource allocation to adapt dynamically to different problem sizes. The compute units are organized in a two-dimensional array structure that maintains high computation speed while allowing flexible configuration of M, N, and K dimensions to match different matrix multiplication requirements.
3Productivity
If large matrices are processed using traditional methods, then the computation is performed sequentially, but the computation time is long and efficiency is low
Solution Approach 1:
The patent segments the matrix multiplication into multiple independent compute units that operate in parallel. Each compute unit processes a specific block of the result matrix, enabling simultaneous computation of multiple elements. This parallel segmentation dramatically improves computation efficiency by utilizing all compute units concurrently, rather than processing elements sequentially as in traditional methods.
Solution Approach 2:
The patent combines multiple compute units into a unified parallel processing system where each unit contributes to the overall matrix multiplication result. The compute units are merged through a coordinated control mechanism that manages data flow and accumulation, achieving high computation efficiency by combining the power of multiple processing elements working simultaneously on different portions of the same computational task.
Data Source
AI summary
Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.