Matrix Multiplication Peripheral With Memory Swapping

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Solution Overview

Problem

Existing microcontrollers struggle with executing complex matrix multiplication operations, leading to processing burdens and system errors, especially when real-time output is required, as they are often busy with higher priority functions.

Innovation Solution

A peripheral device with a weight memory, input memory, multiplier, accumulator, and output memory, controlled by a sequencer, performs matrix multiplication operations independently, allowing the microcontroller to manage overall system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If matrix multiplication operations are executed on the microcontroller, then processing capability is improved, but system reliability deteriorates due to processing burden and errors

Engineering Contradiction:
Improveprocessing capabilityVSAvoidsystem reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system is divided into two functional segments: the microcontroller handles high-level system control and coordination, while the peripheral device handles specific matrix multiplication operations. This segmentation allows each component to operate within its optimal capabilities, improving overall system reliability while maintaining processing capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A peripheral device acts as an intermediary between the microcontroller and the matrix multiplication task. This intermediary handles the computationally intensive operations, freeing the microcontroller from processing burdens and reducing system errors while maintaining overall processing capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If matrix multiplication is implemented in software on the microcontroller, then flexibility is improved, but processing speed deteriorates due to slow and repetitive execution

Engineering Contradiction:
ImproveflexibilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The software-based matrix multiplication implementation is replaced with a hardware-based peripheral device. This substitution transitions from a software-controlled mechanical/electronic system to a dedicated hardware system, dramatically improving processing speed while the peripheral remains programmable to maintain flexibility.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If the microcontroller services higher priority functions, then system responsiveness is improved, but matrix multiplication execution deteriorates due to missed real-time output

Engineering Contradiction:
Improvesystem responsivenessVSAvoidreal-time output generation
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system divides responsibilities by segmenting real-time critical operations (matrix multiplication) from general system control. The peripheral device is dedicated to real-time matrix operations, ensuring they complete regardless of microcontroller interrupt priorities, while the microcontroller handles other system functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The peripheral device operates autonomously to perform matrix multiplication operations without requiring continuous microcontroller intervention. It can service its own real-time output requirements independently, allowing the microcontroller to prioritize other system functions while real-time matrix operations continue uninterrupted.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12517849B2System and methods for matrix multiplication
Publication Date: 2026.01.06 MICROCHIP TECHNOLOGY INC
  • US12517849B2 patent drawing
  • US12517849B2 patent drawing
  • US12517849B2 patent drawing

AI summary

A peripheral device for matrix multiplication including a weight memory, an input memory, a multiplier, an accumulator, an output memory and a sequencer to generate signals to drive the input memory and the output memory and to generate an interrupt signal. The weight memory may be loaded with weights and biases for a matrix multiplication operation, and the multiplier and accumulator may implement the multiply and accumulator operations for a matrix multiplication operation. Data may be swapped between the input memory and output memory to reduce the memory required for matrix multiplication operations.