Hardware Matrix Transpose via Quadrant Swapping
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Solution Overview
Problem
Existing hardware circuits cannot directly perform matrix transpose operations, which are required in certain neural network computations, leading to processing delays due to the need for off-chip data transfer.
Innovation Solution
A special-purpose hardware circuit with a matrix computation unit is designed to perform neural network inferences by generating instructions that allow it to transpose neural network matrices through a series of operations, including subdividing matrices and swapping quadrants, without directly supporting matrix transpose operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a special-purpose hardware circuit without direct matrix transpose support is used, then device complexity is reduced and manufacturing is simplified, but processing time increases due to indirect transpose operations
Solution Approach 1:
The matrix transpose operation is segmented into multiple smaller sub-operations. The matrix is divided into blocks, and the transpose is performed by systematically swapping corresponding blocks across different regions. This segmentation allows the operation to be completed through multiple simpler steps rather than requiring a single complex transpose instruction, thus resolving the contradiction between hardware simplicity and processing efficiency.
Solution Approach 2:
The hardware circuit performs preliminary data reorganization and block swapping operations before the actual matrix computation is needed. By pre-processing the matrix data into the required transposed format through systematic block exchanges, the circuit eliminates the need for time-consuming transpose operations during critical computation phases, thereby reducing overall processing time while maintaining hardware simplicity.
2Ease of manufacture
If off-chip data transfer is used for matrix transpose operations, then hardware circuit design is simplified, but processing speed decreases due to data transfer delays
Solution Approach 1:
An intermediary data reorganization mechanism is introduced within the chip that performs block swapping operations. Instead of transferring data off-chip for transpose operations, the intermediary system rearranges data blocks in-place using controlled exchange operations between different memory regions or processing units on the chip. This eliminates off-chip transfer delays while keeping the hardware design relatively simple through the use of this intermediate reorganization layer.
3Device complexity
If matrix transpose operations are performed through software or off-chip processing, then hardware architecture remains simple, but productivity decreases due to additional processing steps
Solution Approach 1:
The hardware circuit implements dynamic block swapping capabilities that can adaptively reorganize matrix data in real-time. Instead of static hardware designed for a single operation, the circuit dynamically exchanges data blocks between different regions based on the specific transpose requirements. This dynamic reorganization capability enables the simple hardware architecture to perform transpose operations efficiently, maintaining both architectural simplicity and high processing throughput.
Solution Approach 2:
The matrix transpose operation is integrated into the continuous data flow of neural network processing. Block swapping and reorganization operations are performed continuously as part of the computation pipeline rather than as separate discrete steps. This continuity ensures that the hardware remains actively productive throughout the process, eliminating idle time and maintaining high throughput while using a relatively simple architecture.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium. In one aspect, a method includes the actions of receiving a request to perform computations for a neural network on a hardware circuit having a matrix computation unit, the request specifying a transpose operation to be performed on a first neural network matrix; and generating instructions that when executed by the hardware circuit cause the hardware circuit to transpose the first neural network matrix by performing first operations, wherein the first operations include repeatedly performing the following second operations: for a current subdivision of the first neural network matrix that divides the first neural network matrix into one or more current submatrices, updating the first neural network matrix by swapping an upper right quadrant and a lower left quadrant of each current submatrix, and subdividing each current submatrix into respective new submatrices to update the current subdivision.