MBCFET Gate Spacer and Etch Blocking Pattern Design
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling density and improving current control while effectively suppressing the short channel effect, which affects the performance and reliability of multi-gate transistors.
Innovation Solution
A semiconductor device design featuring a multi-bridge channel field effect transistor (MBCFET) with a specific structure including a lower pattern, sheet patterns, gate structures, source/drain patterns, and etch blocking patterns, where the gate spacer has an inner sidewall and a connection sidewall, and the source/drain pattern includes a semiconductor liner layer and filling layer, enhancing the facet surface contact and etch blocking capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor scaling is performed to increase density, then device density improves, but short channel effect suppression becomes more difficult
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional multi-gate structures (FinFET, nanowire, MBCFET) where the gate wraps around the channel in multiple dimensions. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short channel effects while enabling continued scaling and higher device density.
Solution Approach 2:
The multi-bridge channel field effect transistor (MBCFET) employs nested channel structures where multiple bridge channels are stacked vertically and connected through through-silicon holes. This nesting arrangement increases the effective channel width and device density while maintaining excellent electrostatic control through the surrounding gate structures, thereby suppressing short channel effects.
2Reliability
If gate length is increased to suppress short channel effect, then short channel effect suppression improves, but current control capability deteriorates
Solution Approach 1:
Instead of increasing gate length in one dimension, the patent utilizes multi-dimensional gate wrapping structures where the gate extends around the channel in multiple directions. This provides enhanced electrostatic control that suppresses short channel effects without requiring increased gate length, thereby maintaining superior current control capability.
Solution Approach 2:
The channel is divided into multiple segmented regions (FinFET channels, nanowire segments, or MBCFET bridge channels) that are independently controlled by surrounding gate structures. This segmentation allows each segment to be effectively controlled with shorter gate lengths while collectively providing the necessary current control capability.
3Ease of manufacture
If conventional source/drain structure is used in multi-gate transistor, then manufacturing simplicity is maintained, but facet surface contact and etch blocking capabilities are insufficient
Solution Approach 1:
The patent introduces an etch blocking layer that is deposited preliminarily on the facet surfaces of the source/drain regions before subsequent processing steps. This preliminary action ensures proper etch blocking capability and facet surface contact are established early in the manufacturing process, enabling precise control of material deposition and etching while maintaining overall manufacturing simplicity.
Solution Approach 2:
The etch blocking layer serves as an intermediary material between the source/drain regions and subsequent processing layers. This intermediary layer provides the necessary facet surface contact and etch blocking capabilities, facilitating precise manufacturing control without complicating the overall fabrication process.
Data Source
AI summary
A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.