MBC Transistor Strain Engineering for Higher Carrier Mobility
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Solution Overview
Problem
Existing semiconductor devices, particularly multi-bridge-channel (MBC) transistors, face challenges in achieving desired performance such as higher drive capacity and switching speed as they scale down, especially in enhancing electron mobility in N-type transistors.
Innovation Solution
A method involving forming a fin-shaped structure with interleaved channel and sacrificial layers, recessing source/drain regions, performing pre-amorphization implantation, applying a tensile stress film, and annealing to recrystallize the substrate, creating dislocations along the (111) plane to enhance electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MBC transistors are scaled down to increase functional density, then gate control and short-channel effects are improved, but carrier mobility and drive capacity deteriorate
Solution Approach 1:
The patent applies parameter changes by introducing controlled dislocations with specific crystallographic orientations ((111) plane) and configurations into the channel region. These dislocations modify the lattice structure to induce tensile strain, which enhances carrier mobility without compromising the scaled-down gate control achieved in MBC transistors.
Solution Approach 2:
The patent implements local quality by creating dislocations specifically in certain regions of the channel while maintaining the overall MBC structure. The dislocations are strategically positioned to provide localized strain enhancement in the channel region where carrier mobility needs improvement, without affecting other critical areas of the scaled-down device.
2Manufacturing precision
If MBC transistors are scaled down to increase functional density, then gate-channel coupling is improved, but drive capacity deteriorates
Solution Approach 1:
The patent changes physical parameters by introducing dislocations that create tensile strain in the channel region. This strain modifies the band structure and increases carrier velocity, thereby enhancing drive capacity while the scaled-down geometry maintains strong gate-channel coupling through improved electrostatic control.
Solution Approach 2:
The patent effectively creates a composite structure by combining the scaled-down MBC transistor geometry with intentionally introduced dislocation structures. The dislocations act as a strain-inducing component within the channel region, creating a composite system that leverages both the electrostatic benefits of scaling and the mobility enhancement from strain.
3Ease of manufacture
If conventional fabrication processes are used for scaled MBC devices, then manufacturing simplicity is maintained, but performance requirements are not met
Solution Approach 1:
The patent applies preliminary action by introducing dislocations into the channel region before final device operation. This pre-established strain structure ensures that carrier mobility enhancement is already in place before the device begins operation, allowing conventional fabrication processes to be used without requiring complex post-fabrication strain induction steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves carrier mobility, resulting in higher drive capacity and switching speed of semiconductor devices by maintaining stressed lattice configurations and facilitating dislocation growth in the source/drain regions.
Implementation Method 1
performing a pre-amorphization implantation (PAI) process to amorphize a portion of the substrate exposed by the source/drain opening
Implementation Method 2
performing an annealing process to recrystallize the amorphized portion of the substrate. The recrystallized portion of the substrate includes dislocations
Implementation Method 3
forming a tensile stress film over the substrate... maintaining stressed lattice configurations to enhance electron mobility
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor method includes forming a fin-shaped structure extending from a substrate, the fin-shaped structure includes a number of channel layers interleaved by a number of sacrificial layers, recessing a source/drain region to form a source/drain opening, performing a PAI process to amorphize a portion of the substrate exposed by the source/drain opening, forming a tensile stress film over the substrate, performing an annealing process to recrystallize the portion of the substrate, the recrystallized portion of the substrate includes dislocations, forming an epitaxial source/drain feature over the source/drain opening, and forming a gate structure wrapping around each of the plurality of channel layers. By performing the above operations, dislocations are controllably and intentionally formed and carrier mobility in the number of channel layers may be advantageously enhanced, leading to improved device performance.