MBCFET Source/Drain Contact Extension Into Isolation Regions

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Solution Overview

Problem

Current semiconductor devices face challenges in achieving high integration and electrical stability as device sizes decrease, particularly in maintaining efficient current flow and capacitance in multi-bridge channel field effect transistors (MBCFETs).

Innovation Solution

The semiconductor device design includes extending at least a part of the source/drain contact into the element isolation region within a multi-bridge channel field effect transistor (MBCFET) structure, enhancing current flow and performance by optimizing the layout and structure of fin-shaped patterns, nanowires, and gate electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device size is scaled down for high integration, then manufacturing cost is reduced and quality is improved, but electrical stability and current flow efficiency deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The source/drain contact is extended from a purely planar configuration into the vertical dimension by allowing it to protrude into the element isolation region. This three-dimensional contact structure increases the effective contact area and provides additional current flow paths without increasing the planar device footprint, thereby maintaining electrical stability during size scaling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The element isolation region is designed to accommodate the protruding source/drain contact in advance. By pre-configuring the isolation region to receive the extended contact, the design ensures proper electrical isolation and mechanical support before the contact is formed, preventing short circuits and ensuring reliable current flow in scaled-down devices.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If device size is reduced, then integration density increases, but capacitance increases and current flow efficiency decreases

Engineering Contradiction:
Improveintegration densityVSAvoidcapacitance
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

By extending the source/drain contact vertically into the element isolation region, the design increases the effective contact area without increasing the planar dimensions. This reduces the specific capacitance (capacitance per unit area) and provides more efficient current flow paths, reducing energy loss in scaled-down high-density devices.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If source/drain contact is extended into element isolation region, then current flow is improved and electrical stability is enhanced, but device structure complexity increases

Engineering Contradiction:
Improveelectrical stabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The element isolation region serves dual functions: it provides electrical isolation between adjacent devices and simultaneously accommodates the extended source/drain contact. This multi-functional design improves current flow and electrical stability without requiring additional separate structures, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11837638B2Semiconductor device
Publication Date: 2023.12.05 SAMSUNG ELECTRONICS CO LTD
  • US11837638B2 patent drawing
  • US11837638B2 patent drawing
  • US11837638B2 patent drawing

AI summary

A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.