MBCFET Source/Drain Epitaxy Layout for Lower Leakage Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face limitations in integration and performance due to the size reduction of planar metal oxide semiconductor field-effect transistors (MOSFETs), necessitating the development of three-dimensional (3D) channel structures like FinFETs, but existing designs struggle with optimal electrical characteristics and leakage current.
Innovation Solution
A semiconductor device with a gate-all-around type field effect transistor (MBCFET) structure, featuring a source/drain region with epitaxial layers and a gate structure that includes multiple overlapping gate portions, where the epitaxial layers have specific horizontal lengths and crystal plane orientations to enhance electrical characteristics and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar metal oxide semiconductor field-effect transistors are reduced in size to increase integration, then device integration increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional FinFET channel structure, utilizing the vertical dimension to maintain effective channel length and control while reducing planar footprint. This dimensional change allows continued scaling without proportional degradation of operating characteristics.
Solution Approach 2:
The channel is segmented into multiple fins extending vertically, creating multiple independent conduction paths. This segmentation increases the effective channel width within a smaller planar area, improving integration density while maintaining electrical performance through multiple parallel channels.
2Ease of manufacture
If conventional source/drain structures are used in FinFETs, then device fabrication is simpler, but leakage current increases
Solution Approach 1:
The source and drain regions are selectively doped with different impurity concentrations and types in different areas. High-concentration doping is applied locally at the interface with channel layers to reduce leakage, while other regions maintain appropriate doping for carrier injection and extraction, optimizing both performance and manufacturability.
Solution Approach 2:
The patent modifies doping concentration parameters in the source/drain regions, creating high-concentration doped areas adjacent to channel layers to form effective barriers against leakage current, while maintaining manufacturable doping profiles through standard semiconductor processing techniques.
3Reliability
If epitaxial layers with extended horizontal lengths are used, then electrical characteristics improve, but device area increases
Solution Approach 1:
The epitaxial layers extend primarily in the vertical direction rather than horizontally, utilizing the z-axis to achieve the necessary material thickness and electrical properties without increasing the planar device footprint. This vertical extension maintains electrical performance while minimizing area occupation.
Solution Approach 2:
The epitaxial layers are positioned within and around the gate structure, nesting the source/drain regions efficiently within the overall device footprint. This nested arrangement maximizes the use of vertical space and minimizes horizontal area requirements.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: an active region extending in a first direction on a substrate, a plurality of channel layers spaced apart from each other in a vertical direction, a gate structure enclosing the plurality of channel layers, respectively, and a source/drain region contacting the plurality of channel layers. The source/drain region includes a first epitaxial layer extending to contact the plurality of channel layers, and a second epitaxial layer on the first epitaxial layer. A surface in which the first epitaxial layer and the second epitaxial layer contact each other includes: first surfaces having a first slope; second surfaces having a second slope, different from the first slope; first bent portions between the first surfaces and the second surfaces; and a second bent portion in which the second surfaces meet.