MBIST Fault Indicators for ECC-Aware In-Field Memory Testing
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Solution Overview
Problem
Current MBIST control units lack sufficient diagnostic visibility during in-field testing, leading to false customer returns and increased ppm failure risk due to undetected single bit errors correctable by ECC, especially as feature sizes decrease.
Innovation Solution
Implementing an MBIST controller with Failure per Memory (FPM) and ECC Fail Detection (EFD) registers to distinguish between single and multiple bit errors, generating enhanced in-field test status indicators (ift_status) that are stored without software intervention, allowing for improved diagnostic visibility and error classification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If MBIST control units perform in-field testing without enhanced diagnostic capabilities, then the testing process remains simple, but diagnostic visibility is insufficient leading to false returns and increased ppm failure risk
Solution Approach 1:
The MBIST control unit segments the diagnostic information into distinct registers: FPM register for failure indicators and EFD register for ECC failure detection. This segmentation allows precise classification of error types (single bit vs. multiple bit errors) while maintaining modular architecture that doesn't significantly increase overall complexity.
Solution Approach 2:
The patent introduces intermediary status indicators (ift_status) that mediate between the MBIST control unit and external diagnostic systems. These indicators provide enhanced diagnostic visibility by translating internal test results into externally interpretable status information, enabling accurate differentiation between correctable and uncorrectable errors.
2Reliability
If MBIST fails without distinguishing error types, then the control unit remains simple, but false customer returns increase due to inability to detect correctable single bit errors
Solution Approach 1:
The patent applies local quality by providing different diagnostic depths for different error conditions. The FPM register provides detailed failure indicators for each memory location, while the EFD register specifically tracks ECC-related failures. This localized diagnostic quality allows accurate distinction between single bit errors (correctable) and multiple bit errors (uncorrectable) without requiring complex analysis of all possible failure modes.
Solution Approach 2:
The MBIST control unit implements feedback mechanisms through the FPM and EFD registers that continuously monitor and report on error conditions. This feedback enables the system to distinguish between transient single bit errors (which may be correctable by ECC) and permanent multiple bit errors, improving reliability of failure detection while maintaining manageable complexity through structured feedback loops.
3Loss of information
If enhanced diagnostic registers are added to MBIST controller, then diagnostic visibility improves, but register storage requirements increase
Solution Approach 1:
The patent extracts only the essential diagnostic information needed for error classification into dedicated registers. The FPM register extracts failure indicators specific to each memory location, while the EFD register extracts ECC failure status. By taking out only these critical diagnostic elements rather than storing all possible test data, the system achieves enhanced diagnostic visibility with minimal increase in storage requirements.
Solution Approach 2:
The patent changes the parameter representation from raw test data to processed diagnostic indicators. Instead of storing complete test results, the system transforms information into binary failure indicators (0/1) in the FPM and EFD registers. This parameter transformation reduces storage requirements while maintaining sufficient diagnostic information for distinguishing between error types and making accurate failure detection.
Data Source
AI summary
A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.