MBIST Pattern Mask Register Reduces Test Time

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Solution Overview

Problem

The existing memory built-in self-test (MBIST) processes require extensive test time due to the need to run all patterns twice, once during the repair mode and once during the pass-fail mode, with little optimization for patterns that do not generate repairs, leading to inefficiencies and increased tester time for data logging.

Innovation Solution

Incorporating a pattern mask register that masks non-failing patterns during the repair mode and updates in real-time, allowing only patterns with unique fails to be run in the pass-fail mode, thereby reducing test time and eliminating the need for tester involvement in data reprogramming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all patterns are executed twice (once during repair mode and once during pass-fail mode), then thorough testing coverage is achieved, but test time increases significantly

Engineering Contradiction:
Improvetesting coverageVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by executing all test patterns during the repair mode first to identify failing patterns. The fail status register captures which patterns failed during this initial execution. Then, during the pass-fail mode, only the patterns that failed in the repair mode are re-executed. This preliminary identification of failing patterns allows the system to avoid re-executing patterns that would have passed anyway, thereby reducing total test time while maintaining thorough testing coverage for the problematic patterns.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If fail information is logged to the tester for analysis, then accurate fail identification is achieved, but tester time and complexity increase

Engineering Contradiction:
Improvefail identification accuracyVSAvoidtester involvement
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling the MBIST engine to automatically identify and track failing patterns internally using the fail status register, without requiring external tester intervention for data collection and analysis. The pattern mask register automatically updates based on the fail status, and the system autonomously determines which patterns to re-execute in pass-fail mode. This self-service mechanism maintains accurate fail identification while eliminating the need for complex tester involvement in data logging and analysis.

Inventive Principle:
Principle #25Self-service

3Productivity

If patterns are re-executed in pass-fail mode based on unique fails, then test time is reduced, but the system complexity increases

Engineering Contradiction:
Improvetest efficiencyVSAvoidcontrol logic
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the fail status register and pattern mask register to serve multiple functions. The fail status register not only tracks which patterns failed but also directly controls the pattern mask register, which in turn determines which patterns are re-executed in pass-fail mode. This multi-functional design allows a single register structure to handle both fail identification and test pattern selection, reducing the need for separate complex control logic while improving test efficiency through targeted re-execution of failing patterns.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10490296B2Memory built-in self-test (MBIST) test time reduction
Publication Date: 2019.11.26 MARVELL ASIA PTE LTD
  • US10490296B2 patent drawing
  • US10490296B2 patent drawing
  • US10490296B2 patent drawing

AI summary

Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.