Master-Slave MBIST Ring Architecture for Parallel Memory Testing
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Solution Overview
Problem
The increasing complexity of semiconductor devices with multiple memory arrays leads to longer power-up times and higher power draw during Memory Built-In Self-Test (MBIST), posing challenges for portable devices and requiring scalable and efficient testing solutions.
Innovation Solution
A master/slave MBIST architecture with a ring configuration of MBIST Data Path Interfaces allows for concurrent or serial testing of memory arrays, reducing power consumption and test time through modular design and a handshake protocol, enabling flexible trade-offs between power usage and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple memory arrays are tested in parallel, then test time is reduced, but power draw increases
Solution Approach 1:
The patent divides the MBIST testing system into multiple independent slave controllers, each responsible for testing specific memory arrays. This segmentation allows parallel testing of multiple memory arrays simultaneously, reducing total test time while enabling selective activation of slave controllers to manage power consumption.
Solution Approach 2:
The patent implements a dynamic master/slave architecture where the master controller can selectively activate slave controllers based on testing requirements. This dynamic configuration allows the system to adjust the number of active testing units, balancing between test speed and power consumption according to operational needs.
2Adaptability or versatility
If more memory arrays are added to a microprocessor, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent designs slave controllers that can be configured to test different types of memory arrays (L1 cache, L2 cache, LRU, CRQ) through a universal testing mechanism. This multi-functionality allows the same slave controller architecture to handle various memory types, reducing the need for specialized control logic for each memory array type.
Solution Approach 2:
By segmenting the testing control into independent slave controllers, each managing specific memory arrays, the patent reduces the complexity burden on a central control unit. Each slave controller is simpler in design but collectively provides comprehensive testing capability for all memory types.
3Quantity of substance
If memory arrays are spread over larger chip area, then capacity is increased, but routing complexity increases
Solution Approach 1:
The patent assigns specific memory arrays to specific slave controllers, creating localized testing domains. This segmentation reduces the routing distance and complexity for test signals by confining them to smaller, dedicated paths between slave controllers and their associated memory arrays, rather than requiring long routes across the entire chip.
Data Source
AI summary
A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.