MBIST Status Registers for ECC-Aware In-Field RAM Diagnostics
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Solution Overview
Problem
Current MBIST control units lack sufficient diagnostic visibility during in-field testing, leading to false customer returns and increased ppm failure risk due to undetected single bit errors correctable by ECC, especially as feature sizes decrease.
Innovation Solution
Implementing an MBIST controller with enhanced diagnostic capabilities, including Failure per Memory (FPM) and ECC Fail Detection (EFD) registers to distinguish between single and multiple bit errors, generating in-field test status indicators (ift_status) that are stored without software intervention, and utilizing a local or central STCU to manage these indicators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MBIST control units perform in-field testing, then memory reliability can be verified, but diagnostic visibility is insufficient leading to false failure indications
Solution Approach 1:
The diagnostic information is segmented into distinct categories: single bit error indicators and multiple bit error indicators. This segmentation allows the system to differentiate between correctable and uncorrectable errors, providing precise diagnostic visibility while maintaining memory reliability verification.
Solution Approach 2:
The patent introduces intermediary status indicators (ift_status) that mediate between the MBIST testing process and the final failure determination. These indicators serve as an intermediate layer that provides detailed diagnostic information about error types before concluding a failure, resolving the contradiction between reliability verification and diagnostic visibility.
2Reliability
If MBIST fails due to single bit errors correctable by ECC, then memory can still function, but current MBIST cannot distinguish this leading to false returns
Solution Approach 1:
The patent applies local quality by providing different diagnostic information for different error types. The system tracks and reports single bit errors separately from multiple bit errors, allowing precise measurement of failure conditions. This enables the system to distinguish between errors that compromise functionality and those that do not, improving both reliability verification and measurement precision.
3Quantity of substance
If feature sizes decrease, then device density increases, but ppm failure risk increases due to reduced diagnostic capability
Solution Approach 1:
The patent implements feedback mechanisms through continuous monitoring and reporting of error types during MBIST testing. The system provides feedback about single bit versus multiple bit errors, enabling better reliability assessment as device density increases. This feedback loop allows for accurate ppm failure risk calculation even as feature sizes decrease and diagnostic capabilities become more challenging.
Data Source
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AI summary
A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.