At-Speed MCM Interconnect Testing via Die Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current testing methods for multichip module (MCM) interconnects, such as boundary scan testing, are inadequate for detecting delay defects, cross-talk, and simultaneous switching noise, as they require manual and error-prone test case creation and are insufficient for at-speed testing, especially when dealing with multiple fault types and clocking variations between dies.
Innovation Solution
A multi-die chip module configuration with separate test controllers for each die, allowing one die to be in shift mode and the other in capture mode, enabling at-speed testing of interconnects without the delay inherent in traditional boundary scan testing, using a scan chain with modified boundary scan cells and a clocking scheme that accounts for clock uncertainty between dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional boundary scan testing is used for MCM interconnect testing, then the testing infrastructure is simple and reused, but the testing speed is slow and cannot detect delay defects or simultaneous switching noise
Solution Approach 1:
The patent segments the testing operation into two distinct modes: shift mode for loading test patterns and capture mode for capturing responses. This segmentation allows one die to be in shift mode while another is in capture mode, enabling parallel operation and eliminating the sequential delay inherent in traditional boundary scan testing, thus achieving at-speed testing capability.
Solution Approach 2:
The patent introduces dynamic mode switching capability where test controllers can dynamically transition between shift mode and capture mode. This dynamic operation allows the system to adapt its state based on testing requirements, enabling high-speed at-speed testing while maintaining the flexibility to use slower boundary scan mode when needed, effectively resolving the speed-complexity contradiction.
2Reliability
If manual test case creation is used for MCM interfaces, then comprehensive fault coverage can be targeted, but the process is tedious and error-prone
Solution Approach 1:
The patent implements self-service through automatic test case generation and execution. The test controllers automatically generate appropriate test patterns, manage mode transitions, and capture responses without manual intervention. This automation maintains comprehensive fault coverage while eliminating the tedious and error-prone manual test case creation process.
Solution Approach 2:
The patent incorporates feedback mechanisms where test responses are automatically captured, analyzed, and used to guide subsequent testing operations. The system provides real-time feedback on interconnect health status, enabling adaptive test case generation that ensures comprehensive fault coverage while reducing manual effort through intelligent automation.
3Manufacturing precision
If separate characterization is performed for each die I/O, then interface requirements are met, but MCM interconnect testing becomes complex and time-consuming
Solution Approach 1:
The patent merges the testing operations of multiple dies by coordinating their test controllers to operate in complementary modes. One die's output is directly connected to another die's input through the interconnect, allowing simultaneous shift and capture operations. This merging approach maintains precise interface characterization while dramatically reducing testing time through parallel operation.
Solution Approach 2:
The patent performs preliminary setup by configuring the test controllers and establishing the shift/capture mode distribution before actual testing begins. This preliminary configuration ensures that interface characterization requirements are met from the start, and subsequent testing can proceed efficiently without repeated setup overhead, reducing overall testing time while maintaining precision.
Data Source
AI summary
A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.