Multi-chip module solder bump interconnects
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Solution Overview
Problem
Current methods for manufacturing multi-chip modules, such as 3D chip stacks and 2.5D packages, are expensive due to the use of through silicon vias (TSVs) and substrate wires, which are costly and inefficient for achieving high volume and low-cost ultra-small die package assemblies.
Innovation Solution
The method involves forming semiconductor components with different pitch dimensions for connections and interconnecting them using solder bump and pad connections, eliminating the need for TSVs or substrate wires, thereby forming a stacked multi-chip module with improved fabrication techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) and substrate wires are used to interconnect chips in multi-chip modules, then reliable electrical connections between chips are achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent extracts and eliminates the expensive TSV and substrate wire interconnection structures from the MCM design. Instead of using through-silicon vias that require drilling, plating, and filling operations, the invention uses direct chip-to-chip bonding with solder bumps or conductive adhesives applied to pad structures on the chip surfaces, removing the unnecessary intermediate interconnection layers while maintaining electrical connectivity.
Solution Approach 2:
The patent replaces expensive, complex TSV structures with simpler, cheaper pad and bump interconnection structures. The solder bumps or conductive adhesive pads are applied directly to chip surfaces and bonded to corresponding pads on adjacent chips, creating a cost-effective interconnection solution that eliminates the need for expensive TSV fabrication processes while achieving reliable electrical connections.
2Productivity
If chips are stacked in three-dimensional configuration with TSVs, then interconnect density and bandwidth are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the interconnection function into two distinct parts: (1) pad structures formed on chip surfaces during standard CMOS fabrication, and (2) solder bumps or conductive adhesive applications for vertical interconnection. This segmentation allows each component to be optimized independently - pads are integrated into the chip fabrication process while bumps provide the vertical stacking capability, simplifying overall manufacturing compared to monolithic TSV structures.
Solution Approach 2:
The patent transitions from planar two-dimensional interconnections to three-dimensional vertical interconnections by stacking chips with pad-bump-pad structures. Multiple chips are bonded together in a vertical stack, with solder bumps or conductive adhesives providing electrical connections between adjacent chip surfaces. This dimensional transition achieves high interconnect density and bandwidth while using simpler, more manufacturable structures than TSV-based approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and enables the production of high-volume, ultra-small die package assemblies by utilizing solder bump and pad connections, enhancing miniaturization in electronic devices like mobile and IoT devices without the expense of TSVs or substrate wires.
Implementation Method 1
interconnecting them using solder bump and pad connections
Implementation Method 2
adhering a surface of the third semiconductor component to a surface of the second semiconductor component
Data Source
AI summary
A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.