Multi-Chip Package Memory Testing Circuit
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Solution Overview
Problem
In multi-chip packaging, identifying defects in memory chips post-packaging is complex, as damage to memory chips during the process makes it difficult for IC providers to determine if the issue lies with the memory chip or other components, leading to increased testing complications.
Innovation Solution
A method and circuit that perform normal and special read operations on memory cells to verify data integrity, using different word-line voltages and reference currents to distinguish between open and short states, allowing for easy identification of defective memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If normal read operation alone is performed on memory cells, then data integrity can be checked, but it cannot distinguish between open and short states of defective memory chips
Solution Approach 1:
The testing method is segmented into two distinct operations: normal read operation for data integrity checking and special read operation for open/short state detection. This segmentation allows each operation to be optimized for its specific purpose, improving overall measurement precision without overwhelming complexity
Solution Approach 2:
The patent changes the word-line voltage parameter from normal operating voltage to a special voltage level during the special read operation. This parameter change enables the detection of open and short states that cannot be detected during normal read operations, thereby improving defect detection capability
2Measurement precision
If special read operation with different word-line voltages is performed, then open and short states can be distinguished, but testing time and complexity increase
Solution Approach 1:
The normal read operation is performed first as a preliminary check to identify memory cells with data integrity issues. Only cells that fail this preliminary check proceed to the special read operation, reducing the overall testing time by avoiding unnecessary special operations on already-defective cells
Solution Approach 2:
Instead of performing special read operations on all memory cells, the patent applies partial action by only conducting special operations on cells that fail the normal read operation. This reduces testing time while maintaining high defect identification accuracy for cells that actually need detailed examination
3Measurement precision
If multiple read operations are performed on each memory cell, then defect identification accuracy improves, but the testing process becomes more complex
Solution Approach 1:
The testing process is segmented into two distinct phases with clear decision boundaries. The normal read operation serves as the first segment for basic integrity checking, and the special read operation serves as the second segment for detailed defect analysis. This segmentation makes the complex multi-operation process more manageable and easier to implement
Solution Approach 2:
The patent implements feedback control where the result of the normal read operation determines whether to proceed to the special read operation. This feedback mechanism optimizes the testing process by avoiding unnecessary operations and simplifying the overall process complexity while maintaining high detection accuracy
Data Source
AI summary
A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.