Multi Chip Module Noise Isolation via Spacer and Film

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Solution Overview

Problem

In multi-chip modules, the close stacking of semiconductor chips leads to noise interference, particularly from the microcomputer chip affecting the dynamic RAM, due to differences in operational margins and noise generation, which compromises the stability and performance of the DRAM.

Innovation Solution

A stacked multi-chip module structure is implemented with a digital signal processing microcomputer chip on top, a dynamic RAM in the middle, and a non-volatile memory at the bottom, using a spacer to prevent noise propagation from the microcomputer chip to the DRAM, and optimizing the mounting substrate to reduce noise interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the microcomputer chip is mounted on the surface of the DRAM chip to achieve close stacking and miniaturization, then the mounting surface is reduced and integration is enhanced, but the noises generated by the microcomputer chip are transmitted to the DRAM via substrate-parasitic capacitance, worsening the operational margin of the DRAM

Engineering Contradiction:
Improvemounting surface areaVSAvoidnoise interference to DRAM
Core Design Contradiction:
Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

A noise prevention film is introduced as an intermediary layer between the microcomputer chip and the DRAM chip. This film serves as a mediator that blocks the transmission of power source noises from the microcomputer to the DRAM through the substrate-parasitic capacitance, while allowing the chips to remain in close stacked configuration for miniaturization.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention converts the harmful noise transmission path (through substrate-parasitic capacitance) into a beneficial configuration by applying a noise prevention film that specifically targets and blocks the noise frequencies. The same substrate-parasitic capacitance structure that transmits noise is utilized, but the harmful effect is neutralized by the film's frequency-selective blocking properties.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Speed

If chips are closely stacked to shorten wiring distance and enhance device properties, then integration is improved and mounting surface is reduced, but the operational margin of DRAM is worsened due to noise from the microcomputer chip

Engineering Contradiction:
Improvewiring signal transmission speedVSAvoidDRAM operational stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The noise prevention film acts as an intermediary that preserves the close stacking configuration (maintaining short wiring distances for high speed) while simultaneously protecting the DRAM from noise interference. This allows the system to achieve both high-speed signal transmission and reliable DRAM operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The noise prevention film is applied locally to the specific region where noise transmission occurs (between the microcomputer chip and DRAM chip). This localized treatment maintains the overall close stacking structure and short wiring paths while providing targeted noise protection to the vulnerable DRAM region.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7656039B2Multi chip module
Publication Date: 2010.02.02 RENESAS ELECTRONICS CORP
  • US7656039B2 patent drawing
  • US7656039B2 patent drawing
  • US7656039B2 patent drawing

AI summary

The present invention provides a multi chip module which realizes high functions or high performances thereof. A multi chip module is constituted by stacking a first semiconductor chip on which a digital signal processing circuit is mounted, a second semiconductor chip which constitutes a dynamic random access memory, a third semiconductor chip which constitutes a non-volatile memory, and a mounting substrate thus forming the stacked structure. The first semiconductor chip is arranged on an uppermost layer with a spacer interposed on a back surface side thereof. The second semiconductor chip is arranged on the mounting substrate.