MDLL Clock Generator Bias Hold for Fast Phase Lock Recovery
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Solution Overview
Problem
Conventional clock generators using multiplying delay-locked loops (MDLLs) experience increased latency and instability when transitioning from an inactive state due to rapid frequency changes upon reactivation, leading to prolonged phase lock times and increased power consumption.
Innovation Solution
A clock generator with a current supply unit that autonomously provides current to the drain voltage node of the inverter unit, stabilizing the drain voltage and suppressing frequency fluctuations during inactive periods, ensuring rapid frequency stabilization and phase locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage is cut off to reduce power consumption during idle states, then power consumption is reduced, but the oscillator frequency becomes unstable and lock time increases when reactivated
Solution Approach 1:
The patent applies preliminary action by maintaining a predetermined current through the PMOS transistor during idle states before full operation resumes. This preliminary current maintenance prevents the drain voltage from rising to VDD, ensuring that when the reference clock is reapplied, the oscillator is already in a stable state ready for immediate frequency locking, thus avoiding the instability and prolonged lock time that would occur from complete power cutoff
Solution Approach 2:
The patent implements self-service through the current replica cell that automatically replicates and maintains the bias current during idle states without external intervention. The circuit autonomously manages its own bias conditions, keeping the PMOS transistor in a controlled state that enables rapid frequency stabilization when reactivated, eliminating the need for external voltage regulation during transition states
2Stability of the object's composition
If the drain voltage is allowed to rise to supply voltage when power is off, then the circuit is in a stable inactive state, but the oscillator operates at faster frequency than desired upon reactivation increasing lock time
Solution Approach 1:
The patent applies preliminary anti-action by using the current replica cell to counteract the natural tendency of the drain voltage to rise during idle states. By maintaining a predetermined current through the PMOS transistor, the drain voltage is held at a controlled level below VDD, preventing the oscillator from operating at excessively high frequencies when reactivated, thus avoiding increased lock time
Data Source
AI summary
An oscillator configured in a multiplying delay locked loop according to an embodiment includes: a signal input unit configured to apply a reference clock at predetermined intervals; an inverter unit connected to the signal input unit and configured to oscillate and generate an output clock based on a level of a drain voltage dropped from a power supply voltage according to a current supplied by the reference clock; and a current supply unit configured to supply a predetermined current through a node of the drain voltage before the predetermined interval returns after the inverter unit operates, wherein the inverter unit includes a CMOS inverter connected between the drain voltage and ground.