MDLL Clock Selection Using VCO Edge Timing and Divider Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Multiplying Delay Locked Loop (MDLL) architectures require access to internal components of the ring oscillator for multiplexer selection signal generation, limiting control options and stability, and often operate only at full-rate, necessitating half-rate or quarter-rate edge replacements to correct frequency drift.
Innovation Solution
A method for generating a select signal for the MDLL multiplexer that does not rely on internal ring oscillator components, using a select signal generation circuit with D-flip flops and logic gates based on the output of the divider, multiplexed voltage controlled oscillator, and reference signal to achieve full-rate, half-rate, or quarter-rate operations independently of the divider duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If internal components of the ring oscillator are accessed for multiplexer selection signal generation, then the MDLL can be implemented, but the control options are limited and the design is restricted to specific oscillator configurations
Solution Approach 1:
The patent extracts the multiplexer selection signal generation from the internal components of the ring oscillator. Instead of accessing internal nodes within the oscillator, the invention uses only the output signal of the ring oscillator combined with a reference signal to generate the selection signal. This extraction principle removes the dependency on internal component access while maintaining the MDLL functionality.
Solution Approach 2:
The patent creates a universal selection signal generation mechanism that works with different ring oscillator configurations (3-stage, 5-stage, differential, non-differential) without requiring specific internal component access. The selection signal is generated universally from the oscillator output and reference signal, making the MDLL adaptable to various oscillator designs.
2Reliability
If the MDLL operates only at full-rate, then the implementation is simpler, but frequency drift cannot be tracked and corrected effectively
Solution Approach 1:
The patent implements a dynamic selection signal generation system that can adapt its operating rate (full-rate, half-rate, or quarter-rate) based on the specific application requirements. The selection signal generation circuit is designed to be flexible, allowing the MDLL to switch between different replacement rates to track and correct frequency drift while maintaining system stability.
Solution Approach 2:
The patent changes the temporal parameter of the selection signal generation by implementing edge replacement at different rates (full-rate, half-rate, quarter-rate). This parameter change allows the system to balance between correction effectiveness and system complexity, enabling the MDLL to track frequency drift at the appropriate rate without oversimplifying or overcomplicating the design.
3Reliability
If special conditions like differential ring oscillator with skewed rise and fall times are required, then specific architectures work, but the design flexibility is reduced
Solution Approach 1:
The patent removes the dependency on special oscillator conditions by extracting the selection signal generation from the internal timing characteristics of the ring oscillator. Instead of relying on skewed rise and fall times or differential configurations, the invention generates the selection signal from the oscillator output and reference signal, making the MDLL compatible with various oscillator types without requiring specific timing characteristics.
Data Source
AI summary
There is provided a method for generating a select signal for a multiplexer of a Multiplying Delay Locked Loop (MDLL). The method includes determining that an output of a divider of the MDLL is a high level, determining that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level and inserting a select signal as a select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO in response to determining that the output of the divider has achieved the high level.